Adaptive Equalizer Control for NRZ Jitter Removal in CDR Links

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Solution Overview

Problem

Conventional adaptive equalizers for clock and data recovery circuits in serial communication links require complex circuitry and fail to effectively remove jitter caused by timing misalignment and frequency dispersion in NRZ data.

Innovation Solution

An adaptive equalizer system that adjusts its strength based on timing information from the existing phase detector, using a decoder to determine if the data is over- or under-equalized and adjusting amplifier stages to correct amplitude across frequencies, thereby removing jitter without additional circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional adaptive equalizers use analog comparators or digital comparators with ADC to examine eye diagrams, then equalization capability is improved, but device complexity and hardware resources increase significantly

Engineering Contradiction:
Improveequalization capabilityVSAvoidcircuitry complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts only the timing information from the phase detector output instead of using the full eye diagram examination approach. By taking out just the essential timing data and frequency pattern information, the system achieves effective equalization without requiring complex analog comparators or ADC circuits.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The existing phase detector in the CDR circuit is made to serve dual purposes: both clock recovery and equalization control. By utilizing the phase detector's existing timing information output, the system eliminates the need for separate equalization measurement circuits, making the existing components serve multiple functions.

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If conventional equalizers attempt to equalize NRZ data with different amplitudes at different frequencies, then amplitude equalization is improved, but jitter removal effectiveness deteriorates

Engineering Contradiction:
Improveamplitude equalizationVSAvoidjitter removal effectiveness
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent implements dynamic adjustment of equalizer strength based on real-time frequency pattern detection. The system continuously monitors whether high-frequency or low-frequency patterns are present in the input data and dynamically adjusts the equalizer gain accordingly, allowing the equalization characteristics to adapt to the actual data being transmitted rather than using fixed equalization parameters.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the equalizer strength parameter based on detected frequency patterns. When high-frequency patterns are detected, the equalizer strength is increased to compensate for high-frequency attenuation; when low-frequency patterns are detected, the equalizer strength is decreased. This parameter adjustment resolves the contradiction by optimizing both amplitude equalization and jitter removal for the specific data pattern present.

Inventive Principle:
Principle #35Parameter changes

3Speed

If equalizer strength is adjusted rapidly to remove jitter, then jitter removal speed is improved, but equalization smoothness deteriorates due to response to abrupt timing changes

Engineering Contradiction:
Improvejitter removal speedVSAvoidequalization smoothness
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The system uses periodic frequency pattern detection to control equalizer adjustments. By detecting patterns over multiple data transitions and adjusting equalizer strength based on accumulated pattern information rather than instantaneous timing variations, the system achieves smooth equalization while maintaining effective jitter removal. The periodic nature of the adjustment prevents rapid, abrupt changes.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7916780B2Adaptive equalizer for use with clock and data recovery circuit of serial communication link
Publication Date: 2011.03.29 SILICON IMAGE INC
  • US7916780B2 patent drawing
  • US7916780B2 patent drawing
  • US7916780B2 patent drawing

AI summary

An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.