Adaptive Equalizer Circuit With Adjustable Pole Frequency Peaking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing equalizer circuits fail to provide adjustable gain boosts within 0 dB-15 dB for varying channel attenuations due to differences in protocols and rates, leading to excessive power consumption and inadequate compensation.

Innovation Solution

An equalizer circuit with an adjustable active inductor component, RC network, and control mechanism that adjusts performance parameters to dynamically change dominant and non-dominant poles, allowing for flexible frequency peaking adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If frequency peaking is designed as 10 GHz with maximum gain boost at 15 dB, then USB 4.0 channel attenuation is compensated, but gain boost at USB 3.2 Nyquist frequency (5 GHz) is far less than 15 dB, leading to limited application to serious channel attenuation

Engineering Contradiction:
Improvechannel attenuation compensationVSAvoidprotocol compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic adjustment of the equalizer circuit by making the dominant pole and non-dominant pole frequencies可调 (adjustable). The control component dynamically changes the frequencies of the dominant pole and non-dominant pole based on different protocol requirements, enabling the equalizer to adapt to both USB 4.0 (10 GHz) and USB 3.2 (5 GHz) scenarios, thereby resolving the contradiction between reliability for a specific protocol and adaptability across multiple protocols.

Inventive Principle:
Principle #15Dynamics

2Reliability

If frequency peaking is designed as 5 GHz with maximum gain boost at 15 dB, then USB 3.2 channel attenuation is compensated, but gain boost at 10 GHz is much greater than 15 dB, causing excessive power consumption

Engineering Contradiction:
Improvechannel attenuation compensationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent employs dynamic pole frequency adjustment to match the equalizer's gain boost characteristics to the actual channel attenuation requirements. When operating at USB 3.2 rates, the dominant pole is positioned at 5 GHz to provide appropriate compensation without excessive power consumption. When operating at USB 4.0 rates, the dominant pole is shifted to 10 GHz. This dynamic adaptation eliminates the need for excessive power consumption while maintaining reliable channel attenuation compensation across different protocols.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If gain boost is designed to be adjustable within 0 dB-15 dB, then long and short channels are covered, but when frequency peaking is fixed, not all gain boosts can be achieved within this range for different protocols

Engineering Contradiction:
Improvegain boost adjustabilityVSAvoidcompensation accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent achieves both gain boost adjustability and compensation accuracy through dynamic pole frequency adjustment. The control component adjusts not only the gain boost magnitude but also the frequencies of the dominant and non-dominant poles based on protocol requirements and channel characteristics. This dual adjustment mechanism ensures that the equalizer can accurately compensate for channel attenuation across the full 0 dB-15 dB range while maintaining reliability for different protocols and channel lengths.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes multiple parameters simultaneously - both the gain boost level and the pole frequencies - to achieve accurate compensation. By adjusting the frequencies of the dominant and non-dominant poles along with the gain boost, the equalizer can precisely match the channel attenuation characteristics for different protocols and channel conditions, thereby resolving the contradiction between adaptability and compensation accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250358157A1Equalizer Circuit
Publication Date: 2025.11.20 ANALOGIX CHINA SEMICON
  • US20250358157A1 patent drawing
  • US20250358157A1 patent drawing
  • US20250358157A1 patent drawing

AI summary

Disclosed in the disclosure is an equalizer circuit. The equalizer circuit includes a current source component, a resistance-capacitance (RC) network, and a differential transistor pair, where the current source component is electrically connected to the RC network, and the RC network is electrically connected to the differential transistor pair; and the equalizer circuit further includes an adjustable active inductor component electrically connected to a first transistor and a second transistor of the differential transistor pair separately; and a control component electrically connected to the current source component, the RC network, and the adjustable active inductor component separately and configured to change frequencies of a dominant pole and a non-dominant pole of the equalizer circuit by adjusting performance parameters of the current source component, the RC network, and the adjustable active inductor component.