Adaptive Erase Threshold for Non-Volatile Memory Cells

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Solution Overview

Problem

As memory cells decrease in size and memory arrays increase in density, maintaining data integrity becomes challenging due to issues with programming and erasing operations, particularly with the increasing number of program-erase cycles affecting the threshold voltage distributions and erase efficiency.

Innovation Solution

The implementation of an adaptive threshold number system that adjusts based on the number of program-erase cycles or erase-verify loops to determine the completion of erase operations, allowing for more stringent criteria at lower cycle counts and relaxing criteria as cycles increase, thereby reducing erase failures and over-erasure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a fixed threshold number is used for erase verification, then the erase operation completes quickly, but erase failures increase as program-erase cycles increase

Engineering Contradiction:
Improveerase operation speedVSAvoiderase operation success rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the threshold number adaptive rather than fixed. The threshold number changes dynamically based on the program-erase cycle count, allowing the system to adjust verification criteria as memory cells age and degradation occurs, thus maintaining both speed and reliability across different operational stages

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of threshold number based on program-erase cycle count. By modifying this critical parameter adaptively, the system responds to memory cell degradation over time, ensuring reliable erase verification while maintaining operational efficiency throughout the memory device's lifecycle

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If a stringent erase verification criterion is used, then data integrity is maintained, but erase operation time increases

Engineering Contradiction:
Improveerase verification accuracyVSAvoiderase operation duration
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The verification criterion dynamically adjusts based on program-erase cycle count. For newer memory cells with lower cycle counts, more stringent criteria ensure high verification accuracy. As cycle counts increase and cells degrade, the criteria adaptively relaxes to prevent excessive time consumption while maintaining adequate verification standards

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent modifies the verification threshold parameter according to the program-erase cycle count, balancing verification accuracy and operation time. This parameter adaptation allows the system to optimize the trade-off between ensuring data integrity and minimizing erase operation duration under different aging conditions

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If memory density is increased, then storage capacity improves, but data integrity maintenance becomes more difficult

Engineering Contradiction:
Improvememory storage capacityVSAvoiddata integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent addresses the density-integrity trade-off by implementing adaptive threshold adjustment based on program-erase cycle counts. This parameter change strategy compensates for the increased vulnerability of high-density memory cells, maintaining data integrity despite the challenges posed by smaller cell sizes and higher storage capacity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240029804A1Adaptive fail bits threshold number for erasing non-volatile memory
Publication Date: 2024.01.25 SANDISK TECHNOLOGIES LLC
  • US20240029804A1 patent drawing
  • US20240029804A1 patent drawing
  • US20240029804A1 patent drawing

AI summary

An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining a threshold number based on the first count, and determining whether the erase operation passed or failed based on the threshold number.