Adaptive Erase Voltage Control for NAND Flash Memory
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Solution Overview
Problem
In NAND flash memory, precise setting of the next erase voltage after soft erasure is challenging due to varying threshold voltage distributions, which affects data retention and increases erasure time.
Innovation Solution
A semiconductor storage device that includes a memory cell array and a control circuit, which reads data from a selected word line, calculates the number of memory cells exceeding a read level, performs simultaneous erasure using a first erase voltage, and determines a second erase voltage based on the number of cells exceeding a verify level, allowing for precise adjustment of the erase voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erasure is performed deeply to reduce erasure time, then erasure speed is improved, but cell stress increases and data retention deteriorates
Solution Approach 1:
The patent applies dynamics by making the erase voltage adjustable and adaptive rather than fixed. The control circuit dynamically selects from multiple erase voltage levels (first erase voltage for initial erasure, second erase voltage for subsequent erasures) based on the erasure state of memory cells, allowing the system to optimize between speed and cell stress for each specific condition.
Solution Approach 2:
The patent changes the parameter of erase voltage from a single fixed value to multiple selectable values. By introducing different erase voltage levels (higher first erase voltage and lower second erase voltage) and selectively applying them based on verification results, the system can adjust the erasure process to balance speed and reliability.
2Loss of time
If erasure voltage is increased to reduce erasure cycles, then erasure time is reduced, but cell stress and degradation increase
Solution Approach 1:
The system dynamically adjusts the erase voltage applied to memory cells based on their erasure state. The control circuit applies a higher first erase voltage initially to reduce time, then switches to a lower second erase voltage for remaining cells, adapting the voltage level to minimize stress while maintaining efficiency.
Solution Approach 2:
The patent segments the erasure process into multiple phases with different voltage levels. Instead of applying a single high voltage to all cells uniformly, the system divides the erasure operation into stages: initial erasure with higher voltage, verification, and subsequent erasure with lower voltage, treating different cell groups differently based on their state.
3Reliability
If soft erasure is performed with low erase voltage to reduce cell stress, then cell degradation is reduced, but erasure time increases
Solution Approach 1:
The control circuit dynamically selects between higher and lower erase voltages based on the verification results. When memory cells are not fully erased after initial low-voltage soft erasure, the system switches to higher voltage to complete the erasure quickly, thus adapting the voltage level to balance reliability and speed for each specific case.
Solution Approach 2:
The patent implements periodic action through repeated cycles of erasure and verification. The system performs erasure with one voltage level, verifies the erasure state, and if necessary, performs additional erasure with a different voltage level. This periodic verification and adjustment cycle ensures both reliability and efficiency.
4Manufacturing precision
If multiple erasure operations are performed to achieve precise erasure, then erasure precision is improved, but the number of erasure pulses increases and cell stress increases
Solution Approach 1:
The patent changes the erase voltage parameter between different erasure operations. By using a higher first erase voltage for initial erasure and a lower second erase voltage for subsequent erasures, the system achieves precise erasure control while reducing the total number of pulses needed compared to using only low voltage throughout.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is monitored, and an erase voltage is set based on the monitored results. Thus, the erase voltage can be precisely set without depending on the threshold voltage distribution of the memory cell before the erasure.