Adaptive Erase Voltage Control for Nonvolatile Memory Reliability
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Solution Overview
Problem
As semiconductor manufacturing advances, high integration and increased capacity in storage devices lead to new reliability issues, such as data damage, degrading the reliability of nonvolatile memory devices. There is a need for a method and device to improve the reliability of these devices.
Innovation Solution
A nonvolatile memory device with a memory cell array, row decoder circuit, page buffer circuit, and control circuit that repeatedly performs an erase loop with adaptive erase voltage control based on the results of erase verification, adjusting the voltage according to the number of failed or passed memory cells to optimize the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration and higher capacity are implemented in storage devices, then production cost is reduced and storage capacity is increased, but reliability is degraded due to data damage
Solution Approach 1:
The patent implements a feedback mechanism where the control circuit monitors erase verification results from memory cells and dynamically adjusts the erase voltage for subsequent erase loops. The control circuit counts the number of memory cells that fail or pass erase verification and uses this information to determine whether to increase, decrease, or maintain the current erase voltage level, creating a closed-loop control system that adapts to actual memory cell conditions
Solution Approach 2:
The erase voltage is transformed from a static, fixed parameter to a dynamic, adjustable parameter that changes based on real-time verification results. The control circuit modifies the erase voltage level adaptively during different erase loops, allowing the system to respond to varying memory cell states and achieve more precise erase control
2Reliability
If erase voltage is increased to ensure complete erasure, then erase reliability is improved, but memory cell deterioration is accelerated
Solution Approach 1:
The patent dynamically changes the erase voltage parameter based on verification results. Instead of using a consistently high erase voltage, the control circuit adjusts the voltage level up or down depending on whether memory cells are erasing properly, allowing the system to use the minimum necessary voltage to achieve complete erasure while avoiding excessive voltage that would cause deterioration
Solution Approach 2:
The control circuit monitors erase verification results in advance and adjusts the erase voltage proactively to prevent both incomplete erasure and excessive erasure. By detecting trends in verification failures or successes, the system can cushion against potential problems before they cause data damage or cell deterioration
3Reliability
If adaptive erase voltage control is implemented, then reliability is improved, but device complexity is increased
Solution Approach 1:
The control circuit performs self-service by autonomously monitoring its own erase operations through verification results and automatically adjusting the erase voltage without external intervention. The system uses its existing verification infrastructure to generate control signals, making the adaptive control mechanism relatively simple to implement
Solution Approach 2:
The control circuit performs multiple functions: it manages the overall erase operation, counts verification results, determines voltage adjustment decisions, and controls the erase voltage output. By consolidating these functions in a single control circuit, the patent avoids the need for separate dedicated circuits for each function, reducing overall complexity
Data Source
AI summary
A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.