Adaptive Erase Voltage for Non-Volatile Memory Disturbance
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Solution Overview
Problem
Non-volatile memory cells, such as EEPROMs, experience cycling degradation due to accumulated trapped charges, leading to increased threshold voltages and eventual errors, limiting the number of programming cycles and causing variations in erase behavior.
Innovation Solution
Adjusting the disturb voltage based on the characteristics of memory cells, such as usage type and application profile, to minimize the impact on electrically coupled cells during erase operations, allowing for optimized erase voltage levels that reduce disturbance across the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase pulse is used to erase the memory cell, then the erase operation is simple and fast, but the cycling endurance deteriorates and other memory cells or pages are disturbed
Solution Approach 1:
The patent applies local quality by differentiating between memory cells based on their threshold voltage characteristics. Memory cells are divided into groups (first and second groups) with different erase voltage requirements. The controller selectively applies different erase pulse voltages to different groups of cells, allowing optimized erase operations that protect cells with higher threshold voltages while maintaining efficient erasure of cells with lower threshold voltages, thereby preserving cycling endurance without significantly reducing erase speed
Solution Approach 2:
The patent implements dynamics by making the erase voltage adaptive rather than fixed. The controller dynamically adjusts the erase pulse voltage based on the characteristics of the memory cell group being erased. For the first group of cells with lower threshold voltages, a first erase voltage is applied, while for the second group with higher threshold voltages, a second (higher) erase voltage is applied. This dynamic voltage adjustment allows the system to maintain high productivity for easy-to-erase cells while ensuring reliable erasure of harder-to-erase cells, thus balancing speed and endurance
2Productivity
If blocks of cells are erased simultaneously, then the erase operation is efficient, but the threshold voltage distribution varies and cycling degradation increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple groups of cells based on their threshold voltage characteristics. The controller identifies and separates memory cells into a first group (with lower threshold voltages) and a second group (with higher threshold voltages). This segmentation allows the system to erase different groups with appropriately optimized voltages, preventing excessive cycling degradation in cells with higher threshold voltages while maintaining efficient erasure of cells with lower threshold voltages, thus preserving threshold voltage stability across the array
Solution Approach 2:
The patent implements parameter changes by varying the erase voltage parameter based on cell group characteristics. Instead of using a uniform erase voltage for all cells, the controller changes the voltage parameter dynamically: applying a first erase voltage to the first group of cells and a second (higher) erase voltage to the second group. This parameter adjustment optimizes the erase operation for each group's specific threshold voltage distribution, reducing unnecessary cycling stress on cells with higher threshold voltages while maintaining efficient erasure, thereby stabilizing threshold voltage across the memory array over time
3Reliability
If the erase voltage is increased to ensure complete erasure, then the erase operation becomes more reliable, but the disturbance to other memory cells increases
Solution Approach 1:
The patent applies local quality by tailoring the erase voltage to the specific characteristics of each memory cell group. The controller determines which cells belong to the first group (lower threshold voltages) and which belong to the second group (higher threshold voltages). When erasing, the system applies a first erase voltage to the first group and a second (higher) erase voltage only to the second group. This localized voltage application ensures reliable erasure of cells with higher threshold voltages without unnecessarily subjecting all cells to high voltage stress, thereby minimizing disturbance to cells that do not require such high voltages for erasure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the disturbance on non-erased memory cells, prolongs the endurance of memory devices by minimizing cycling degradation, and allows for more efficient erase operations by tailoring the erase voltage to the specific memory types, thereby extending the device's usable cycle count.
Implementation Method 1
a strong electric field from a well 101 to a control gate (CG) 102 is employed to initiate Fowler-Nordheim tunneling of electrons from a floating gate (FG) 104 to the well 101
Data Source
AI summary
A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted.