Adaptive Erase Verify Voltage for NAND Flash Memory

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Solution Overview

Problem

NAND-type flash memory experiences an over-erase state due to shifting threshold voltage distribution, leading to increased stress on memory cells and deterioration of the gate insulating film, which affects data reliability.

Innovation Solution

The nonvolatile semiconductor memory device implements an adaptive erase operation by adjusting the erase verify voltage based on the number of erase pulse applications, relaxing judgment criteria to prevent over-erase states and maintaining a stable threshold voltage distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If erase pulse application operation is executed multiple times to ensure complete erase, then erase reliability is improved, but threshold voltage distribution shifts negatively causing over-erase state

Engineering Contradiction:
Improveerase reliabilityVSAvoidthreshold voltage distribution
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies dynamics by making the erase verify voltage variable rather than fixed. The control circuit adjusts the erase verify voltage based on the number of times the erase pulse application operation has been executed. As the erase operation progresses and the threshold voltage distribution shifts negatively, the erase verify voltage is increased to maintain appropriate verification criteria, preventing over-erase while ensuring complete erase reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of erase verify voltage dynamically during the erase operation. The control circuit monitors the execution count of erase pulse application operations and相应地 adjusts the erase verify voltage level. This parameter change allows the verification threshold to adapt to the shifting threshold voltage distribution, resolving the contradiction between ensuring complete erase and preventing over-erase state.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If strict erase verification criteria are maintained, then data reliability is improved, but over-erase states occur increasing stress on memory cells

Engineering Contradiction:
Improvedata reliabilityVSAvoidstress on memory cells
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent makes the verification criteria dynamic by adjusting the erase verify voltage based on the progression of the erase operation. Instead of maintaining strictly fixed verification criteria that would cause over-erase, the system adapts the verification threshold to match the actual state of the memory cells, reducing unnecessary stress while maintaining data reliability through appropriate verification at each stage.

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If erase verify voltage is kept constant, then operation simplicity is maintained, but it cannot adapt to threshold voltage distribution shifts

Engineering Contradiction:
Improveoperation simplicityVSAvoidadaptability to threshold voltage shifts
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent transitions from a static erase verify voltage to a dynamic one that automatically adjusts based on the number of erase pulse applications. The control circuit incorporates logic to monitor the erase progression and相应地 modify the verify voltage, providing adaptability to threshold voltage distribution shifts while maintaining operational simplicity through automated control.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by using the execution count of erase pulse application operations as input to determine the appropriate erase verify voltage. The control circuit receives feedback about the erase progression state and adjusts the verify voltage accordingly, enabling the system to adapt to threshold voltage distribution shifts while maintaining simple operation through closed-loop control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8976597B2Electrically rewriteable nonvolatile semiconductor memory device
Publication Date: 2015.03.10 KIOXIA CORP
  • US8976597B2 patent drawing
  • US8976597B2 patent drawing
  • US8976597B2 patent drawing

AI summary

A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.