Adaptive Error Correction Coding for Flash Memory Integrity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flash memory systems face challenges in efficiently providing redundancy for error correction encoded data, particularly in maintaining data integrity as the integrity of flash memory components degrades over time, leading to increased bit error rates and the need for adaptive error correction coding to ensure data protection.

Innovation Solution

The system employs error correction coding with variable code rates based on the integrity of flash memory blocks, using a binary exclusive-or operation to generate redundancy data without padding, which is written separately from encoded codewords, allowing for recovery of lost codewords using redundancy data and other decodable codewords.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction coding is applied to flash memory data, then data integrity is improved, but processing resources and power consumption increase

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing resources and power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the code rate parameter of the error correction coding based on the integrity status of flash memory blocks. When blocks are healthy, lower code rates are used to minimize processing overhead. When blocks show signs of degradation, higher code rates are applied to maintain data integrity. This adaptive parameter adjustment resolves the contradiction by optimizing the balance between error correction capability and processing resource consumption.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If redundancy data is generated for each codeword, then data protection is improved, but storage space and processing complexity increase

Engineering Contradiction:
Improvedata protectionVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system segments the flash memory into multiple blocks with different integrity characteristics and applies error correction coding independently to each segment. This allows the system to generate redundancy data selectively based on the specific needs of each block, rather than uniformly across all data. The segmentation approach reduces overall processing complexity by focusing computational resources only where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically determines the code rate for each codeword based on real-time assessment of block integrity. This dynamic adaptation allows the system to adjust redundancy generation in response to changing storage conditions, maintaining optimal data protection while minimizing unnecessary processing complexity in healthy blocks.

Inventive Principle:
Principle #15Dynamics

3Reliability

If variable code rates are used based on block integrity, then data protection efficiency is improved, but system complexity increases

Engineering Contradiction:
Improvedata protection efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements a feedback mechanism that continuously monitors block integrity and uses this information to adjust code rates for subsequent error correction coding operations. The integrity assessment feedback loop enables the system to automatically adapt to degradation patterns, maintaining optimal data protection efficiency without requiring complex manual configuration or intervention.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10198313B2Redundancy of error correction encoded data in a storage system
Publication Date: 2019.02.05 WESTERN DIGITAL TECHNOLOGIES INC
  • US10198313B2 patent drawing
  • US10198313B2 patent drawing
  • US10198313B2 patent drawing

AI summary

A device that provides for redundancy of error correction encoded data includes at least one processor circuit. The at least one processor circuit is configured to perform error correction encoding on data items to generate corresponding codewords, where at least one of the data items may have a different length than at least one other of the data items and each of the codewords is the same length. The at least one processor circuit is further configured to generate a redundancy data item based at least in part on the codewords. The at least one processor circuit is further configured to write the codewords and the redundancy data item to separate blocks of at least one flash memory circuit.