Adaptive Filter DCO Synchronization for Fast PLL Lock
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Solution Overview
Problem
Traditional phase locked loops (PLLs) face challenges in achieving quick frequency lock with low jitter and are complex, making them unsuitable for circuit integration.
Innovation Solution
A digital phase locked loop with an adaptively adjustable low pass filter, where the bandwidth is calculated using the expression B=⌈Ep⌉·C, allowing for dynamic adjustment based on phase error, enabling faster lock acquisition with reduced jitter and simpler integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a low bandwidth filter is used to reduce jitter, then jitter is reduced, but lock acquisition time increases significantly
Solution Approach 1:
The filter bandwidth is made dynamically adjustable rather than fixed. The system switches between a first bandwidth value during acquisition and a second bandwidth value during tracking, allowing the filter characteristics to adapt to different operational phases and resolve the contradiction between fast acquisition and low jitter.
Solution Approach 2:
The bandwidth parameter of the filter is changed based on operational phase. During frequency acquisition, a larger bandwidth is used to allow faster response, while during frequency tracking, a smaller bandwidth is used to minimize jitter, thus resolving the time-jitter tradeoff through parameter adaptation.
2Measurement precision
If a complex PLL implementation is used to achieve precise frequency lock, then frequency lock precision is improved, but device complexity increases
Solution Approach 1:
The PLL functionality is segmented into distinct operational modes (acquisition and tracking) with different filter bandwidth settings. This segmentation allows each mode to be optimized independently, achieving precise frequency lock without requiring a continuously complex system design.
Solution Approach 2:
A single filter structure is used for both acquisition and tracking phases, with only the bandwidth parameter changing. This multi-functional approach eliminates the need for separate filter circuits for each phase, reducing overall device complexity while maintaining frequency lock precision.
Data Source
AI summary
A digital phase locked loop has a digital controlled oscillator, a feedback loop coupled to the output of said digital controlled oscillator, a phase detector for comparing a feedback signal from said feedback loop with a reference signal to produce a phase error signal, and a low pass filter for filtering the phase error signal for controlling said digital controlled oscillator. A bandwidth calculation unit calculates the required filter bandwidth based on the phase error. The bandwidth calculation unit then controls the bandwidth of said low pass filter, which is thus adaptively adjusted in accordance with the phase error.