Adaptive FIR Filter Limiting for Overshoot-Free Image Signals
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Solution Overview
Problem
Conventional low pass digital filters in digital image signal processing suffer from overshoot and undershoot issues due to negative filter coefficients and fixed maximum/minimum value limitations, leading to unstable image reception and degraded quality.
Innovation Solution
A filter device comprising a digital filter with unit delay elements and a maximum/minimum detector circuit that dynamically adjusts the limiter circuit to detect and limit output values based on detected maximum and minimum values from multiple stages, eliminating overshoot and undershoot without increasing chip area complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a low pass FIR digital filter is used for filtering high frequency components, then frequency characteristics are improved, but overshoot and undershoot occur in the output signal
Solution Approach 1:
The patent applies dynamics by making the maximum and minimum values used for limiting dynamically variable rather than fixed. The maximum value is updated based on the maximum values of internal latch data from the shift register, and the minimum value is updated based on the minimum values of internal latch data. This dynamic adjustment allows the limiter circuit to adapt to changing signal conditions, effectively suppressing overshoot and undershoot while maintaining good frequency characteristics.
2Device complexity
If fixed maximum and minimum values are used in the limiter circuit, then circuit complexity is reduced, but overshoot and undershoot cannot be completely eliminated
Solution Approach 1:
The patent transforms the static fixed-value limiting approach into a dynamic adaptive limiting approach. The maximum value and minimum value are no longer constants but are updated based on the actual signal characteristics (internal latch data) from the shift register. This dynamic adaptation enables complete elimination of overshoot and undershoot while adding only minimal circuit complexity through simple comparison and selection logic.
3Measurement precision
If the filter length is increased to improve filtering performance, then frequency characteristics are improved, but chip area increases
Solution Approach 1:
The patent uses a relatively short filter length (5 stages) rather than a long filter length, which would provide better frequency characteristics but occupy more chip area. By combining this short filter with the dynamic limiting circuit that uses internal latch data, the patent achieves effective suppression of overshoot and undershoot without requiring a large filter length, thus maintaining small chip area while still providing adequate filtering performance.
Data Source
AI summary
A filter device comprises a digital filter, a maximum/minimum detector circuit, and a limiter circuit. The digital filter includes unit delay elements chained together and having M stages (M is an integer equal to or larger than two) for shifting an n-bit (n is a positive integer) digital input signal; n multiplier circuits for multiplying output signals from the unit delay elements at the respective stages by predetermined filter coefficients, respectively; and adder circuits chained together and having (M−1) stages for summing output signals from the respective multiplier circuits to supply a filtered output signal. The maximum/minimum detector circuit detects a maximum value detection signal and a minimum value detection signal in the output signals supplied from the unit delay elements. The limiter circuit limits a minimum value of the filtered output signal based on the maximum value detection signal, and limits a minimum value of the filtered output signal based on the minimum value detection signal.