Adaptive Fixed-Point CNN Accelerator for Power-Constrained Edge Devices
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Solution Overview
Problem
Convolutional neural networks (CNNs) require high computational power and energy consumption, especially for real-time object detection and segmentation in videos, which is a challenge for mobile devices and other power-constrained systems, as traditional implementations using high-accuracy floating-point values are inefficient.
Innovation Solution
A method and digital hardware device that accelerates CNN computations using a novel adaptive fixed-point representation and approximate operations, eliminating the need for explicit multiplication units by employing lookup tables, adders, and shifters, while optimizing digital arithmetic units to control the tradeoff between power and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional floating-point computation is used for CNN, then computation accuracy is improved, but power consumption increases
Solution Approach 1:
The patent changes the numerical representation parameter from floating-point to fixed-point format, and introduces adaptive precision control where the precision level is dynamically adjusted based on the specific computational context. This allows the system to use lower precision (reducing power) when high accuracy is not critical, while maintaining higher precision when needed, thus resolving the contradiction between accuracy and power consumption
Solution Approach 2:
The patent implements dynamic precision adaptation where the computational precision is not fixed but adjusted in real-time based on the input data characteristics and computational requirements. This dynamic adjustment allows the system to optimize the trade-off between accuracy and power consumption adaptively throughout the computation process
2Speed
If dedicated digital circuit for NN computation is used, then computation speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the CNN computation into distinct operational phases (convolution, activation, pooling) and implements specialized hardware units for each phase. This segmentation allows parallel processing of different computation stages, improving overall speed while keeping each individual hardware unit relatively simple and manageable in complexity
Solution Approach 2:
The patent designs multi-functional hardware units that can perform different operations (multiplication, accumulation, activation functions) within the same circuit block. This universality reduces the total number of dedicated circuits needed, thereby reducing overall device complexity while maintaining high computation speed through efficient resource utilization
3Productivity
If massive parallelization is used for CNN acceleration, then productivity is improved, but use of energy increases
Solution Approach 1:
The patent implements periodic activation of parallel computation units based on the actual computational workload and data dependencies. Instead of continuously activating all parallel units, the system periodically enables only the necessary units for current computation stages, reducing energy consumption while maintaining high throughput when full parallelization is beneficial
Solution Approach 2:
The patent applies partial parallelization strategies where not all computational units are activated simultaneously, but rather a sufficient subset is enabled to achieve the required throughput. This partial action approach avoids the excessive energy consumption of full parallelization while still providing significant acceleration compared to sequential processing
Data Source
AI summary
A method of processing a layer in a convolutional neural network includes reading a plurality of different subsets of pairs of input vector values and corresponding weight vector values from an on-chip memory, storing the pair values in registers of a plurality of multiplication units, simultaneously processing the different subsets of pairs of values in the registers by multiplying the pairs of values and accumulating the results of the multiplications to obtain an output vector for a current layer. The input vector and the weight vector have floating point values and multiplying the pairs of values comprises adding corresponding pairs of integers in a log domain, and an input value or weight value is released from the on-chip memory after said input value or weight value is no longer needed for calculating non-computed output vector values.