Adaptive Multi-Stage Flash Decoding for Lower Read Latency

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Solution Overview

Problem

Flash memory introduces data errors due to manufacturing variations and aging, which existing error correcting codes like LDPC struggle to address efficiently without adding latency to read operations.

Innovation Solution

A multi-stage decoding operation is executed using a sequence of read-level voltages determined based on previous decoding data, optimizing the order of voltages to prioritize those with higher success rates, thereby reducing the number of stages required to successfully decode data and minimizing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC error correcting codes are employed to correct data errors in flash memory, then error correction capability is improved, but read operation latency increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidread operation latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the read-level voltage sequence adaptive rather than fixed. The sequence is dynamically adjusted based on previous decoding results and memory cell aging states, allowing the system to optimize decoding efficiency in real-time while maintaining robust error correction capability across different operational conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements preliminary action by pre-determining multiple possible read-level voltage sequences before actual decoding operations. Based on the aging state and previous decoding performance, the most appropriate sequence is selected in advance, enabling faster convergence during the decoding process and reducing overall latency

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple read-level voltages are used in multi-stage decoding to handle memory variations, then decoding success rate is improved, but the number of stages and latency increase

Engineering Contradiction:
Improvedecoding success rateVSAvoiddecoding latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by systematically varying read-level voltage parameters across different stages based on memory cell aging characteristics. By adjusting voltage levels and their application sequence according to detected aging states, the system achieves high decoding success rates while minimizing the number of stages required

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback mechanisms where previous decoding results are used to inform and adjust subsequent decoding attempts. The system learns from past decoding outcomes and adapts the read-level voltage sequence accordingly, improving success rates while avoiding redundant decoding stages

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11211949B2Dynamic multi-stage decoding
Publication Date: 2021.12.28 SANDISK TECHNOLOGIES LLC
  • US11211949B2 patent drawing
  • US11211949B2 patent drawing
  • US11211949B2 patent drawing

AI summary

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.