Adaptive Frequency Synthesis for I2S Oversampling Clocks
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Solution Overview
Problem
Existing systems for data communication in embedded and audio systems require external high-frequency master clocks for oversampling, which increase power consumption and can cause electromagnetic interference, and do not efficiently reduce pin count.
Innovation Solution
The integration of an internal frequency synthesizer within IC components to generate adaptive oversampling clocks based on bit depth and oversampling rate, eliminating the need for an external master clock by using a frequency detector and clock generator to produce a synchronous oversampling clock from the I2S interface signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external master clock is used for oversampling in A/D and D/A converters, then the jitter noise requirement is met and audio quality is maintained, but power consumption increases and electromagnetic interference issues occur
Solution Approach 1:
The patent extracts the master clock function from the external domain and relocates it internally within the audio processing device. By integrating a frequency synthesizer that generates the master clock signal from the existing bit clock input, the system eliminates the need for an external master clock input pin while maintaining the required oversampling rate and low jitter performance for high-quality audio conversion.
Solution Approach 2:
The patent makes the bit clock signal serve multiple functions: it acts as both the data synchronization clock for the I2S interface and as the reference signal for generating the master clock through the frequency synthesizer. This multi-functionality eliminates the need for a separate master clock input, reducing pin count and power consumption while maintaining audio quality.
2Productivity
If an external master clock is provided, then the oversampling rate requirement is met, but the pin count increases and system integration efficiency decreases
Solution Approach 1:
The patent merges the master clock generation function with the existing bit clock input by implementing a frequency synthesizer internally. The synthesizer takes the bit clock signal and generates the master clock signal at the required oversampling rate (typically 128x or 256x the bit clock frequency), thereby combining multiple clock functions into a single input pin and reducing overall device complexity.
Solution Approach 2:
The frequency synthesizer acts as an intermediary component that transforms the low-frequency bit clock signal into the high-frequency master clock signal required for oversampling. This intermediary mechanism enables the system to achieve high oversampling rates without requiring direct external provision of the high-frequency clock signal, thus reducing pin count while maintaining productivity.
3Ease of operation
If an external master clock drive circuit is implemented, then the clock signal is provided, but electromagnetic interference and compatibility issues arise
Solution Approach 1:
The patent extracts the master clock drive circuit function from the external interface and relocates it internally within the device. The frequency synthesizer generates the master clock signal using internal circuitry driven by the bit clock, eliminating the need for an external high-frequency clock input and its associated drive circuitry, thereby reducing electromagnetic interference and improving EMI/EMC compatibility.
Solution Approach 2:
The device becomes self-sufficient by generating its own master clock signal internally through the frequency synthesizer using the bit clock as reference. This self-service approach eliminates dependency on external clock sources and their drive circuits, reducing electromagnetic interference while maintaining ease of operation through automatic clock generation.
Data Source
AI summary
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.