Adaptive-Gain Digital LDO Regulator for Uniform Transient Response
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Solution Overview
Problem
Existing analog low dropout (LDO) regulators face challenges such as stability dependence on package parasitic and output pole, minimum dropout issues, and DC offset errors, which affect their performance and scalability with process technologies.
Innovation Solution
A digital low dropout (DLDO) voltage regulator is introduced, utilizing a digital bus to control power-gate transistors, an analog-to-digital converter to generate a digital output, and a controller to manage the transistors, achieving uniform gain and near elimination of DC current paths, with reprogrammable coefficients for tuning and non-linear control features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If analog voltage control is used for LDO regulator gate drive, then the regulator can be implemented with traditional analog architecture, but the circuit does not scale well with process technologies and requires careful design
Solution Approach 1:
The patent replaces the analog voltage control mechanism with a digital control system. A digital-to-analog converter (DAC) generates the control voltage based on digital codes, and an analog-to-digital converter (ADC) provides feedback. This substitution of digital electronics for analog control circuits enables better scalability with process technologies while reducing design complexity.
2Reliability
If head room of 50 mV to 120 mV is provided between input and output voltage, then the LDO regulator can operate normally, but this minimum dropout becomes a challenge when input power supplies are getting lower
Solution Approach 1:
The patent implements dynamic control of the LDO regulator through digital coding. The system uses multiple codes (e.g., code 0 to code N) to dynamically adjust the regulator's operation. This dynamic approach allows the regulator to adapt to varying input voltages and load conditions, enabling normal operation with reduced headroom requirements and improving adaptability to low input voltage scenarios.
Solution Approach 2:
The patent changes the control parameter from fixed analog voltage to digitally controllable parameters. By using digital codes to control the regulator operation, the system can adjust its behavior based on input voltage levels, allowing it to maintain reliable operation with lower headroom and adapt to a wider range of input voltage conditions.
3Reliability
If analog LDO regulator uses dual loop architecture, then regulation function can be achieved, but there are multiple integration and design challenges
Solution Approach 1:
The patent replaces complex analog dual-loop architecture with a digital control system. The digital controller uses ADC for feedback sampling and DAC for control signal generation, simplifying the integration process. This digital approach maintains feedback loop stability while significantly reducing design and integration challenges associated with analog dual-loop circuits.
4Power
If FET array with non-linear transfer function is used, then power can be provided to output node, but the transient response is sharp when code N is low and sluggish when code N is high
Solution Approach 1:
The patent implements feedback control using an ADC to monitor the output voltage and a digital controller to adjust the control signal accordingly. This feedback mechanism compensates for the non-linear transfer function of the FET array, ensuring uniform transient response characteristics across different operating regions and code values while maintaining power delivery capability.
Data Source
AI summary
Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.