Adaptive Gate Bias Sequencing for Stable RF FET Drain Current
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Solution Overview
Problem
Existing RF amplifier technologies face challenges in maintaining consistent drain current and gate bias voltage across varying temperature, time, frequency, and device variations, particularly with LDFETs and N-Channel depletion mode devices, leading to instability and potential damage due to improper sequencing of gate and drain voltages.
Innovation Solution
An adaptive transistor gate bias circuit that senses drain current and automatically adjusts gate voltage to maintain constant drain current, incorporating temperature compensation and a novel sequencer for N-Channel depletion devices to ensure proper voltage sequencing and prevent damage, using components like opto-couplers and thermoelectric devices for temperature sensing and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDFET gate bias voltage is set to establish quiescent current, then the transistor operates in desired region, but the gate bias voltage drifts over temperature, time, input drive, and frequency causing instability
Solution Approach 1:
The patent implements a feedback mechanism where the drain current is sensed and automatically used to adjust the gate bias voltage. This closed-loop system continuously monitors the actual drain current and modifies the gate voltage to compensate for drift caused by temperature, time, input drive, and frequency variations, thereby maintaining stable operation
Solution Approach 2:
The circuit uses the transistor's own drain current as the sensing signal for bias adjustment, eliminating the need for external temperature sensors or complex compensation circuits. The system self-regulates by utilizing its operational parameters directly to control its bias conditions
2Ease of manufacture
If N-Channel depletion device drain voltage is applied before negative gate voltage, then circuit startup is simplified, but drain to source resistance is very low causing short circuit and potential damage
Solution Approach 1:
The patent employs a bias sequencer that applies the negative gate voltage to the N-Channel depletion device before applying the drain voltage. This preliminary action ensures the device is in a high-impedance state before power application, preventing the harmful short circuit condition while maintaining simple circuit startup
3Reliability
If external bias sequencing is used for GaN devices, then proper voltage sequencing is achieved, but the solution is cumbersome and external to the amplifier circuit
Solution Approach 1:
The patent combines the bias sequencing function with the amplifier circuit itself by implementing an internal bias sequencer that is integrated into the amplifier's power supply network. This merging eliminates the need for separate external sequencing equipment while maintaining accurate voltage sequencing, thereby reducing overall system complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures consistent performance across a wide range of temperatures and device variations, preventing damage by ensuring proper voltage sequencing and maintaining constant output power, while reducing power consumption and complexity.
Implementation Method 1
incorporating temperature compensation and a novel sequencer for N-Channel depletion devices to ensure proper voltage sequencing and prevent damage, using components like opto-couplers and thermoelectric devices for temperature sensing and control
Data Source
AI summary
A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.