Adaptive Gate Voltage Circuit for High-Voltage Pad Drivers
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Solution Overview
Problem
Semiconductor devices with advanced technology nodes face challenges in operating with both low internal voltages and high external voltages, leading to potential electrical stress on output driver circuits.
Innovation Solution
Implementing an adaptive gate voltage generation system using PMOS and NMOS transistors configured to switch between different voltage levels, allowing the output driver circuit to operate seamlessly across varying external voltages while maintaining safe operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the output driver circuit is designed for low internal voltage (1.5 V) to match advanced technology nodes, then manufacturing precision and device compatibility are improved, but the circuit cannot directly handle high external voltages (3.3 V) without electrical stress
Solution Approach 1:
The patent introduces an intermediate voltage generation circuit that converts the high external voltage (3.3 V) into a lower intermediate voltage suitable for the output driver circuit's gate control. This intermediary voltage acts as a buffer, allowing the low-voltage-optimized output driver to safely control high-voltage pads without direct exposure to harmful voltage levels, thus resolving the contradiction between manufacturing precision and electrical stress protection
Solution Approach 2:
The patent dynamically changes the voltage parameter applied to the gate of the output driver transistor based on the operating mode. By adjusting the gate voltage to an appropriate intermediate level rather than directly applying the full external voltage, the circuit maintains optimal performance for advanced technology nodes while preventing electrical stress damage, effectively resolving the voltage compatibility contradiction
2Adaptability or versatility
If the output driver circuit directly handles high external voltage (3.3 V), then adaptability to legacy boards is improved, but the internal low-voltage circuitry (1.5 V) suffers from electrical stress and reduced reliability
Solution Approach 1:
The patent segments the voltage handling function into two distinct parts: the output driver transistor that controls the high-voltage pad and the internal low-voltage circuitry that generates control signals. By separating these functions and using an intermediate voltage generation stage, the circuit achieves adaptability to both legacy and modern boards while protecting the internal low-voltage circuitry from electrical stress, thus maintaining reliability
Solution Approach 2:
The intermediate voltage generation circuit serves as a mediator between the high-voltage external environment and the low-voltage internal circuitry. It enables the output driver to interface with legacy 3.3 V boards while preventing harmful voltage levels from reaching the sensitive internal circuitry, thereby maintaining both adaptability and reliability
Data Source
AI summary
A circuit includes a first and second PMOS transistor serially coupled between a high voltage power supply and a pad, a gate of the first PMOS transistor coupled to a first signal from an internal circuit, the first signal configured to switch between a first voltage and the high voltage power supply, a gate and drain of the second PMOS transistor connected to an adaptive control node and the pad, respectively, and a first and second NMOS transistor serially coupled between the pad and a ground, a gate of the first NMOS transistor coupled to a second signal from the internal circuit, the second signal configured to switch between a second voltage and the ground, a gate and drain of the second NMOS transistor connected to the adaptive control node and the pad, respectively, wherein the adaptive control node is configured to switch between the first and second voltage.