Adaptive Glitch Detector Calibration for SoC Temperature Drift
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Solution Overview
Problem
Existing glitch detectors incorporated within system on a chip (SOC) are prone to failure due to temperature variations, as the delay chain's delay settings become less than ideal when the SOC's operating temperature changes, leading to potential missed glitch detection.
Innovation Solution
A glitch detector system with a configurable delay chain and a calibration control circuit that adjusts the number of delay elements based on glitch detection, ensuring optimal delay settings across varying temperatures, and a calibration process that adjusts the delay chain length to maintain effective glitch detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed delay chain is used in the glitch detector, then the device complexity is reduced, but the reliability deteriorates due to temperature variations causing suboptimal delay settings
Solution Approach 1:
The delay chain is made dynamically configurable through a calibration control circuit that adjusts the number of active delay elements based on detected glitches and temperature conditions. This transforms a static, fixed delay chain into a dynamic system that adapts to changing operating conditions, resolving the contradiction between simplicity and reliability.
Solution Approach 2:
The delay chain's effective length is changed as a parameter in response to temperature variations and glitch detections. The calibration control circuit modifies the number of active delay elements, thereby changing the delay parameter to maintain optimal glitch detection performance across different operating conditions.
2Measurement precision
If the delay chain length is increased to improve glitch detection sensitivity, then the measurement precision is improved, but the loss of time increases due to longer delay periods
Solution Approach 1:
The delay chain length is made dynamic rather than fixed. The calibration control circuit adjusts the number of active delay elements in real-time based on temperature and glitch detection needs, allowing the system to optimize the balance between detection sensitivity and time delay for each operating condition.
Solution Approach 2:
The delay parameter is actively adjusted by changing the number of active delay elements in the chain. This parameter change allows the system to achieve optimal detection precision while minimizing unnecessary time delays, as the delay length is adapted to match actual operating conditions rather than being overly conservative.
3Adaptability or versatility
If a calibration process is implemented to adjust delay settings, then the adaptability is improved, but the device complexity increases due to additional control circuits
Solution Approach 1:
The calibration control circuit operates autonomously to adjust the delay chain settings based on glitch detections and temperature conditions. The system self-calibrates without external intervention, with the calibration control circuit monitoring performance and automatically adjusting delay elements to maintain optimal operation across varying conditions.
Solution Approach 2:
A feedback mechanism is implemented where glitch detection results and temperature information are fed back to the calibration control circuit. This feedback loop enables the system to continuously optimize its delay settings based on actual performance, improving adaptability while keeping the control architecture manageable through closed-loop control.
Data Source
AI summary
A glitch detector includes an input flip-flop clocked by a clock signal and having a non-inverting data output, an inverting data output, and a data input receiving input from the inverting data output, the input flip-flop generating a divided version of the clock signal at the non-inverting data output. A configurable delay chain receives the divided version of the clock signal and generates a delayed version of the divided version of the clock signal as a delay output. An intermediate flip-flop clocked by the clock signal has a data input receiving the delay output, the intermediate flip-flop generating an intermediate output as a function of the delay output. A logic circuit receives the divided version of the clock signal and the intermediate output, and generates a glitch detect signal by performing a logical operation on the divided version of the clock signal and the intermediate output.