Adaptive Granularity Row Buffer Cache for Irregular Memory Access
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Solution Overview
Problem
In three-dimensional (3D) stacked dynamic random-access memory (DRAM) systems, caching entire DRAM rows can be inefficient for applications with irregular memory access patterns, leading to increased power consumption and latency due to the long length of DRAM rows and the need for frequent row buffer activations and closings.
Innovation Solution
The implementation of an adaptive-granularity row buffer cache (AG-RB cache) that dynamically adjusts the amount of data transferred to the row buffer cache based on memory access patterns, using a predictor module to determine whether and how much of a DRAM row to cache, and a DRAM-status aware replacement policy to minimize latency, allowing for scalable performance and energy efficiency across various memory behaviors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If entire DRAM rows are cached, then memory access performance is improved, but power consumption increases due to frequent row buffer activations and closings
Solution Approach 1:
The patent divides a DRAM row into multiple segments and caches only the accessed segments rather than the entire row. The row buffer cache is partitioned into multiple row buffer cache lines, each capable of storing a segment of a DRAM row. This segmentation allows the system to cache only the necessary portions of data, reducing the frequency of row buffer activations and closings, thereby improving memory access performance while reducing power consumption.
2Speed
If entire DRAM rows are cached, then memory access performance is improved, but latency increases due to the long length of DRAM rows
Solution Approach 1:
The patent extracts and caches only the specifically accessed segments from the long DRAM rows rather than caching the entire row. By identifying and extracting only the necessary data segments that are actually accessed, the system reduces the time required to transfer and cache data, thereby improving memory access performance while reducing latency associated with handling long DRAM rows.
3Loss of energy
If adaptive granularity caching is implemented, then energy efficiency is improved, but device complexity increases due to predictor module and replacement policy
Solution Approach 1:
The patent implements dynamic cache management through a predictor module that adaptively determines which segments to cache based on predicted access patterns, and a replacement policy that dynamically selects which segments to evict. The system dynamically adjusts the granularity and content of cached data based on runtime behavior, allowing it to achieve high energy efficiency through intelligent, adaptive decision-making that manages the complexity of cache operations.
Data Source
AI summary
According to an example, a method for adaptive-granularity row buffer (AG-RB) caching may include determining whether to cache data to a RB cache, and adjusting, by a processor or a memory side logic, an amount of the data to cache to the RB cache for different memory accesses, such as dynamic random-access memory (DRAM) accesses. According to another example, an AG-RB cache apparatus may include a 3D stacked DRAM including a plurality of DRAM dies including one or more DRAM banks, and a logic die including a RB cache. The AG-RB cache apparatus may further include a processor die including a memory controller including a predictor module to determine whether to cache data to the RB cache, and to adjust an amount of the data to cache to the RB cache for different DRAM accesses.