Adaptive Half-Bridge Gate Drive Control for Cross-Current Prevention
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Solution Overview
Problem
In half-bridge circuits with MOSFETs, preventing cross currents while minimizing the delay during which both transistors are blocking is challenging, leading to increased power losses, especially at high switching frequencies.
Innovation Solution
A method where the drive voltage of one transistor is compared with two adaptive threshold values, allowing the other transistor to switch on only after a specified delay, with the threshold values adjusted based on the duration between switching operations to optimize the timing and prevent simultaneous conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long delay T0 is used to prevent cross currents, then the reliability of preventing simultaneous conduction is improved, but the power losses increase due to extended blocking period
Solution Approach 1:
The patent applies dynamics by making the delay period adaptive rather than fixed. The control circuit dynamically adjusts the delay duration based on the actual switching state of the transistors, using feedback signals to optimize the blocking period length, thereby minimizing energy losses while ensuring cross-current prevention.
Solution Approach 2:
The patent implements feedback mechanisms where the switching state of each transistor is monitored and fed back to the control circuit. This feedback enables the control circuit to adjust the delay period T0 in real-time, ensuring that the blocking period is just long enough to prevent cross currents but not excessively long to cause unnecessary power losses.
2Reliability
If the delay period T0 is extended to ensure transistor T1 is blocked, then cross current prevention is improved, but the efficiency of the half-bridge circuit deteriorates due to longer simultaneous blocking
Solution Approach 1:
The patent makes the delay period dynamic and adaptive rather than static. The control circuit continuously monitors transistor switching states and adjusts the delay duration accordingly, ensuring that the blocking period is optimized for each switching cycle, thus maintaining both reliability and efficiency.
Solution Approach 2:
The patent changes the parameter of delay period duration based on operating conditions. By adjusting the length of delay period T0 according to the actual switching behavior of the transistors, the system optimizes the balance between ensuring proper blocking and maintaining circuit efficiency.
3Productivity
If the switching frequency is increased to improve productivity, then the output performance is improved, but the power losses in the blocking period increase significantly
Solution Approach 1:
The patent applies dynamics by making the delay period adaptive to switching frequency and operating conditions. As switching frequency increases, the control circuit adjusts the delay period to be appropriately shorter, preventing the blocking period from becoming excessively long and causing disproportionate power losses at high frequencies.
Solution Approach 2:
The patent changes the delay period parameter in response to switching frequency changes. By dynamically adjusting this parameter based on the operating frequency and transistor switching characteristics, the system minimizes power losses while maintaining effective cross-current prevention across different operating conditions.
Data Source
AI summary
A method is disclosed for controlling a first transistor in a half-bridge circuit which also includes a second transistor. The transistors can be controlled by applying drive voltages to their gates. During a switch-off operation of the second transistor, the amplitude of the drive voltage of the second transistor is compared with a first threshold value and a second threshold value. A switch-on operation for the first transistor is started following a specified first period which begins at a first time when the drive voltage of the second transistor undershoots the first threshold value. The first threshold value is set in accordance with a second period which begins at a second time when the amplitude of the drive voltage of the second transistor undershoots the second threshold value. The second period ends at another time when the first transistor adopts a specified initial operating state during the switch-on operation.