Adaptive Hardware Fault Detection for Automotive SoC
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Solution Overview
Problem
Existing methods for in-field hardware fault detection of automotive system-on-chip (SoC) circuits are inefficient due to resource limitations, missing corner cases, and inability to detect latent defects that arise during field operation, posing functional safety concerns.
Innovation Solution
Implementing an adaptive hardware fault detection system that uses hardware metrics to prioritize and optimize fault injection campaigns, incorporating machine self-learning to generate ranked functional Built-In Self-Test (BIST) tests for proactive detection and continuous improvement of product quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault injection campaigns are performed to ensure reliability and safety of SoC systems, then fault detection capability is improved, but testing time and computational resources are significantly increased
Solution Approach 1:
The patent applies preliminary action by pre-generating comprehensive fault injection test cases during the design verification phase using formal verification tools. These test cases are stored in a database and can be directly applied during field operation without requiring time-consuming real-time analysis, thus resolving the contradiction between thorough fault detection and testing time
Solution Approach 2:
The patent implements dynamics by creating an adaptive fault detection system that dynamically selects and prioritizes test cases based on runtime hardware metrics and detected anomalies. The system adjusts testing intensity and focus based on actual device behavior, combining pre-generated test cases with real-time adaptation to achieve comprehensive fault detection without exhaustive testing
2Reliability
If comprehensive fault injection campaigns are conducted to cover all corner cases, then fault detection coverage is improved, but computational resources and complexity are significantly increased
Solution Approach 1:
The patent applies segmentation by dividing the fault detection process into distinct phases: pre-computation phase where test cases are generated and stored, and runtime phase where specific test cases are selected and executed based on hardware metrics. This segmentation allows comprehensive fault coverage to be achieved without requiring all computational resources to be available simultaneously, reducing peak computational complexity
Solution Approach 2:
The patent implements partial action by using formal verification to generate a superset of possible fault scenarios, then selectively applying only the relevant subset during field operation based on hardware metrics. This approach ensures comprehensive coverage potential while reducing actual computational burden to only what is necessary based on observed device behavior
3Ease of manufacture
If BIST circuits are used for in-field self-testing, then test cost and technician accessibility are improved, but fault coverage and multiple-point latent fault detection are reduced
Solution Approach 1:
The patent merges traditional BIST self-testing capabilities with externally generated fault injection test cases from formal verification. The system combines the advantages of both approaches: the cost-effectiveness and accessibility of BIST with the comprehensive coverage of formal verification-based test cases, achieving both low cost and high fault coverage simultaneously
Solution Approach 2:
The patent introduces an intermediary layer between the BIST circuits and the test patterns. This intermediary selectively applies pre-generated fault injection test cases to the BIST framework, enabling multiple-point latent fault detection while maintaining the self-testing capability and cost benefits of BIST architecture
4Manufacturing precision
If extensive fault injection testing is performed at manufacture, then initial defect detection is improved, but ability to detect latent defects during field operation is reduced
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing a comprehensive library of fault injection test cases during manufacturing. These test cases are prepared in advance using formal verification tools and can be applied during field operation to detect latent defects that may not manifest during initial manufacturing testing, thus resolving the contradiction between initial defect detection and in-field latent defect detection
Data Source
AI summary
A method, system, and architecture (100) for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server (121) which receives specified hardware metric data (131) monitored at an integrated circuit device (110) in the field, identifies prioritized built-in self-test (BIST) fault detection tests (134) based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests (132) to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information (133) identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.