Adaptive Hysteresis Comparator Circuit for Fast Noise-Resistant Switching
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Solution Overview
Problem
Common comparator circuits are susceptible to undesirable rapid output state changes due to small voltage fluctuations from noise, which are not adequately addressed by traditional hysteresis methods, especially in applications requiring fast signal processing.
Innovation Solution
A comparator design incorporating a current mirror with a floating or conducting switch controlled by an inverter output, featuring an asymmetrical input transistor pair and a control transistor, allows for adaptive hysteresis to stabilize threshold voltages and enhance switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hysteresis is applied to prevent output oscillation, then noise robustness is improved, but switching speed decreases
Solution Approach 1:
The patent applies dynamics by making the hysteresis effect adaptive rather than fixed. The third transistor's conductance is dynamically adjusted based on the output signal state, creating variable hysteresis that is strong during transitions for noise immunity but can be reduced for fast signaling. This resolves the contradiction by allowing the system to have both noise robustness and fast switching capability at different times.
Solution Approach 2:
The patent changes the parameter of hysteresis strength by controlling the third transistor's conductance state. When the output transitions, the transistor is conductive providing strong hysteresis for noise immunity. When the output is stable, the transistor can be made floating or less conductive, reducing the hysteresis effect and allowing faster response to new input changes, thus enabling both noise robustness and fast switching.
2Measurement precision
If hysteresis is increased to provide robustness against noise, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the hysteresis function with the existing output stage transistors rather than adding a separate hysteresis circuit. The third transistor is integrated into the current mirror structure, and its conductance is controlled by the output signal itself. This provides precise threshold voltage stability through hysteresis while avoiding the complexity of additional dedicated hysteresis components.
Solution Approach 2:
The hysteresis mechanism is self-regulating through the feedback loop. The output signal automatically controls the third transistor's conductance, which in turn adjusts the hysteresis effect. This self-service approach provides stable threshold voltages without requiring external control circuits or additional complexity, as the system regulates itself based on its own output state.
3Productivity
If asymmetrical input transistor pair is used to enable faster switching, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent deliberately introduces asymmetry in the input transistor pair, making the first and second input transistors different in size or characteristics. This asymmetry is designed to optimize switching speed by allowing one transistor to turn off faster than the other. The controlled asymmetry improves productivity by enabling faster switching while the design accounts for manufacturing variations through the overall circuit topology and feedback mechanism.
Data Source
AI summary
A comparator includes an input stage configured to receive a pair of input signals to generate at least one differential current signal. The comparator further includes an output stage configured to generate an output signal depending on the differential current signal. The output stage includes a current mirror and a node electrically connected to the current mirror. The current mirror includes a first transistor, a second and a third transistor, the second and the third transistors being connected in parallel. The comparator further comprises a gain stage including a first and a second inverter, wherein an output of the first inverter is input to the second inverter. An output of the second inverter is configured to control the third transistor to be in a floating or conducting state.