Adaptive Frequency Synthesis for Internal I2S Oversampling Clocks
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Solution Overview
Problem
Existing data communication systems, particularly in audio applications, face challenges with high power consumption and electromagnetic interference due to external master clock signals required for oversampling, which also increase pin count and reduce system integration efficiency.
Innovation Solution
The integration of an internal frequency synthesizer within IC components to generate adaptive oversampling clocks based on bit depth and oversampling rate, reducing the need for external master clock signals and allowing for local generation of necessary clock signals, such as the left/right clock, from the I2S interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external master clock signals are used for oversampling, then audio quality is maintained through low jitter noise, but power consumption increases and electromagnetic interference occurs
Solution Approach 1:
The patent extracts the master clock generation function from external sources and implements it internally within the audio processing device. The frequency synthesizer generates the master clock signal on-chip, eliminating the need for external master clock inputs and their associated power consumption and EMI issues, while maintaining the required low jitter performance for audio quality
Solution Approach 2:
The device serves itself by generating its own master clock signal through an internal frequency synthesizer that adapts to the I2S interface parameters. The system automatically configures the synthesizer based on detected bit depth and oversampling rate, eliminating dependency on external clock sources and reducing both power consumption and EMI
2Reliability
If external master clock signals are used for oversampling, then clock synchronization is achieved, but pin count increases and system integration efficiency decreases
Solution Approach 1:
The patent removes the external master clock pin requirement by extracting the clock generation function internally. The frequency synthesizer generates the master clock from the existing I2S interface clocks, eliminating the need for additional external clock pins and simplifying the system integration
Solution Approach 2:
The existing I2S interface clocks (bit clock and left/right clock) are made multi-functional by using them as input references for the frequency synthesizer. These clocks serve both their original data synchronization function and as the basis for generating the master clock, eliminating the need for separate external master clock pins
3Speed
If drive circuit of external master clock is used, then high frequency oversampling clock is provided, but electromagnetic interference and compatibility issues arise
Solution Approach 1:
The patent extracts the high frequency clock generation function from external drive circuits and implements it internally using a frequency synthesizer. This eliminates the external drive circuit that causes EMI, while still achieving the required high oversampling clock frequencies through on-chip signal multiplication
Solution Approach 2:
The frequency synthesizer acts as an intermediary that converts the low frequency I2S interface clocks into high frequency oversampling clocks internally. This intermediate conversion process occurs within the chip without requiring external high frequency signal transmission, thereby eliminating EMI and compatibility issues
Data Source
AI summary
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.