Adaptive Inline Polling for Hardware-Accelerated Data Compression

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Solution Overview

Problem

Incorporating a hardware accelerator like QuickAssist Technology (QAT) into CPU systems for data compression faces challenges such as high CPU overhead, increased response latency, and inefficient polling strategies, particularly in scenarios where CPU resources are under pressure, leading to suboptimal performance in deduplication systems.

Innovation Solution

An adaptive inline polling method is introduced, which dynamically adjusts polling intervals based on data pattern characteristics, QAT computing performance, and CPU scheduling latency, reducing QAT response latency and CPU offloading overhead by performing inline polling within the compression thread context, thereby eliminating context switch overhead and optimizing performance across varying workloads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hardware accelerator is used for data compression, then compression performance is improved, but CPU overhead increases

Engineering Contradiction:
Improvecompression performanceVSAvoidCPU overhead
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic polling interval adjustment based on workload characteristics and hardware accelerator completion status. The system transitions from static polling to adaptive polling where the interval is modified in real-time based on queue depth, previous completion times, and system load, thereby optimizing CPU overhead while maintaining compression performance

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms by monitoring hardware accelerator completion status and using this information to adjust subsequent polling behavior. The polling interval is dynamically modified based on feedback from previous polling outcomes, completion times, and queue states, creating a closed-loop control system that balances performance and overhead

Inventive Principle:
Principle #23Feedback

2Loss of time

If polling frequency is increased to reduce response latency, then QAT response latency is reduced, but CPU overhead increases

Engineering Contradiction:
ImproveQAT response latencyVSAvoidCPU overhead
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic polling interval adjustment based on workload characteristics and hardware accelerator completion status. The system transitions from static polling to adaptive polling where the interval is modified in real-time based on queue depth, previous completion times, and system load, thereby optimizing CPU overhead while maintaining compression performance

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the polling interval parameter dynamically based on operating conditions. By adjusting this key parameter according to workload type, data size, and hardware accelerator performance, the system achieves low response latency when needed while reducing CPU overhead during lighter loads

Inventive Principle:
Principle #35Parameter changes

3Productivity

If inline polling is performed within compression thread context, then context switch overhead is eliminated, but polling complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoidpolling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the polling operation with the compression thread execution context. Instead of separating polling and compression into different threads, the system integrates polling checks within the compression thread's flow, eliminating context switches and reducing overhead while managing complexity through careful integration design

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11824567B2Adaptive inline polling of data compression with hardware accelerator
Publication Date: 2023.11.21 EMC IP HLDG CO LLC
  • US11824567B2 patent drawing
  • US11824567B2 patent drawing
  • US11824567B2 patent drawing

AI summary

A computer implemented method of data compression using a hardware accelerator includes submitting a request to compress or decompress a data segment using a compression or decompression thread. The method also includes compressing or decompressing the data segment using a hardware accelerator, and performing inline polling of the hardware accelerator to determine whether the hardware accelerator has completed compressing or decompressing the data segment. The inline polling and the compressing or decompressing are performed in a single thread. The method also includes submitting a wakeup command to a segment thread in response to determining that the hardware accelerator has completed compressing or decompressing the data segment.