Adaptive Input Buffer Switching for LPDDR Speed-Power Tradeoffs
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Solution Overview
Problem
In LPDDR DRAM, there is a need for an automatic and flexible configuration to optimize between power consumption and speed, as the input unit requires high power for high-speed data processing and low power for low-speed data transmission.
Innovation Solution
An input buffer circuit with a detection circuit to determine the working frequency and temperature, and a mode control circuit to switch between double-end differential and single-end CMOS input modes, adjusting bias current and resistance to optimize data processing speed and power consumption based on these parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the input buffer operates in double-end differential mode for high-speed data processing, then data processing speed is improved, but power consumption increases
Solution Approach 1:
The input buffer circuit dynamically switches between double-end differential mode and single-end CMOS mode based on the detected working frequency. The mode control circuit adjusts the operating mode in real-time, enabling the system to use high-performance double-end differential mode when speed is critical and energy-efficient single-end CMOS mode when power consumption is a concern, thus resolving the contradiction between speed and power consumption
Solution Approach 2:
The circuit changes its operating parameters (mode of operation) based on the working frequency detected by the detection circuit. By adjusting the parameter of input buffer mode according to frequency conditions, the system achieves optimal balance between speed and power consumption across different operating scenarios
2Use of energy by moving object
If the input buffer operates in single-end CMOS mode for low power consumption, then power consumption is reduced, but data processing speed decreases
Solution Approach 1:
The system dynamically adapts its operating mode based on real-time frequency detection. When the working frequency indicates low-speed requirements, the mode control circuit switches to single-end CMOS mode for energy efficiency, while automatically transitioning to double-end differential mode when high-speed processing is needed, thus resolving the speed-power tradeoff
3Device complexity
If a fixed configuration is used for the input buffer, then device complexity is reduced, but adaptability to different working conditions decreases
Solution Approach 1:
The input buffer circuit incorporates a detection circuit that automatically detects the working frequency and a mode control circuit that autonomously selects the appropriate operating mode without external intervention. This self-service mechanism enables the system to adapt to different working conditions automatically, achieving high adaptability while maintaining relatively simple device complexity through automated decision-making
Data Source
AI summary
The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode. The single-end CMOS circuit may be configured to a process low-speed data transmission in the single-end CMOS input mode.