Adaptive Instruction Prefetching for Microprocessor Energy Efficiency
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Solution Overview
Problem
Existing microprocessor systems face challenges in reducing code fraction, leading to high energy consumption and performance inefficiencies due to large instruction cache sizes and frequent branch instructions, which result in wasted energy and increased execution time.
Innovation Solution
The Adaptive Code Fraction Reduction Method and System convert native instructions into packed and associative packed normative instructions at compilation time, allowing for concurrent prefetching and fetching of native instructions, reducing the need for instruction cache memory and energy consumption by discarding flow control instructions and optimizing branch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If instruction cache memory size is increased to store more instructions, then instruction cache hit rate is improved, but energy consumption and device area increase
Solution Approach 1:
The patent segments the instruction stream into basic blocks and identifies branch instructions to create targeted prefetch queues. Instead of caching all instructions, only relevant instructions within basic blocks are prefetched and stored in separate queues (sequential queue, branch target queue, loop queue), reducing the overall cache memory requirement while maintaining high hit rates for actually executed instructions.
Solution Approach 2:
The patent performs preliminary analysis of the instruction stream at compile time to identify branch instructions and basic blocks. At runtime, it preliminarily determines the next basic block to execute and pre-fetches only the necessary instructions for that specific block into dedicated queues before execution, avoiding the energy cost of caching and accessing unrelated instructions.
2Productivity
If more instructions are prefetched from memory, then instruction fetch throughput is improved, but instruction cache memory usage and energy consumption increase
Solution Approach 1:
The patent applies local quality by creating different types of prefetch queues with different characteristics for different instruction patterns: sequential queue for linear instruction flow, branch target queue for jumped instructions, and loop queue for repeated basic blocks. Each queue is optimized for its specific purpose, allowing efficient prefetching of only the locally needed instructions rather than bulk prefetching all possible instructions.
Solution Approach 2:
The patent implements dynamic adaptation by monitoring branch prediction outcomes and loop detection results during runtime. The system dynamically adjusts which prefetch queue receives instructions and how many instructions are prefetched based on actual execution patterns, optimizing throughput while adapting to changing program behavior without requiring static allocation of large cache memory.
3Loss of information
If branch instructions are included in prefetch operations, then complete program flow is captured, but prefetch accuracy decreases and unnecessary instructions are fetched
Solution Approach 1:
The patent extracts branch instructions from the regular instruction stream and handles them separately through branch prediction mechanisms. When a branch is predicted to be taken, only the branch target basic block instructions are prefetched into the branch target queue, rather than prefetching all possible branch paths. This extraction of branch handling from linear prefetching eliminates energy waste on instructions that won't be executed while maintaining complete program flow information through intelligent selection.
Solution Approach 2:
The patent uses branch prediction feedback to guide prefetching decisions. The branch prediction unit provides feedback about which branch path is likely to be taken, and this feedback directly controls which instructions are prefetched and where the program counter is set. Loop detection feedback similarly adjusts prefetching behavior to avoid redundant prefetching of already-executed basic blocks, minimizing energy waste while capturing complete necessary program flow.
Data Source
AI summary
A method and system of the instruction packing and scaling are designed for simultaneously enhancing energy efficiency by concurrent and advanced prefetching/fetching instructions via the small and/or banked caches and for improving the performance of microprocessors by reducing the fraction of program and by employing the simple and fast caches. The invention is also designed for converting high fraction code to simplified, branch-reduced, and hidden code during compilation time, for storing packed/scaled code to concurrently accessible the plurality of caches and main memories, and for reverting the code to the native instructions during the instruction prefetch and fetch operations. Consequently, the invention does not forward many flow control instructions including procedure callers/returns and unconditional branches to microprocessors. In particular, the invention accurately prefetches/fetches instructions from the main memories to small, simple, and fast caches, which significantly reduce leakage and dynamic power dissipation, access time, and chip area.