Adaptive Interface Circuit for USB to PCIe Data Transfer

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Solution Overview

Problem

Current USB-to-PCIe adaptive interface techniques experience delays in data transmission due to the NVMe controller's response time, leading to inefficiencies and bandwidth waste during data access operations between a USB host and an NVMe storage device.

Innovation Solution

An adaptive interface circuit is introduced, coupling a USB interface with a PCIe interface, incorporating a UAS protocol processing circuit, a data buffer, and an NVMe protocol processing circuit. The circuit generates NVMe commands and doorbell signals before receiving a write-ready signal, allowing early retrieval of data from the buffer, thereby accelerating data access and reducing bandwidth waste.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the NVMe controller waits for the host to finish transmitting data before retrieving instructions, then data transmission accuracy is ensured, but data access speed deteriorates due to controller response time delay

Engineering Contradiction:
Improvedata access speedVSAvoidcontroller response time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies preliminary action by having the NVMe controller retrieve and execute instructions from the submission queue before the host finishes transmitting data. The controller proactively polls the submission queue and processes available instructions ahead of time, rather than waiting passively for host completion signals. This allows the controller to be ready to process data immediately upon arrival, significantly reducing the response time delay while maintaining data transmission accuracy through proper queue management and completion tracking.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the NVMe controller responds slower to doorbell signals, then system stability is maintained, but transmission bandwidth utilization deteriorates due to idle time

Engineering Contradiction:
Improvebandwidth utilizationVSAvoididle transmission time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements continuity of useful action by establishing a continuous polling mechanism where the NVMe controller continuously monitors the submission queue for new instructions. Instead of idle waiting periods between doorbell signals, the controller maintains active engagement with the queue, retrieving and executing instructions as soon as they become available. This continuous operation eliminates idle transmission time and maximizes bandwidth utilization, while the completion queue mechanism ensures system stability through proper state tracking.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If data is transmitted in smaller chunks to match controller processing speed, then processing completeness is improved, but total transmission time increases

Engineering Contradiction:
Improvedata processing throughputVSAvoidtransmission duration
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent applies segmentation by dividing the data transmission into discrete instruction units organized in the submission queue. Each instruction represents a manageable chunk of work that the controller can process independently. This segmentation allows the controller to process multiple small instructions in rapid succession through continuous polling, rather than waiting for large data blocks. The completion queue similarly segments tracking of processed data, enabling efficient throughput measurement and management without extending total transmission duration.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11138142B2Adaptive interface circuit
Publication Date: 2021.10.05 REALTEK SEMICON CORP
  • US11138142B2 patent drawing
  • US11138142B2 patent drawing
  • US11138142B2 patent drawing

AI summary

Disclosed is an adaptive interface circuit for connecting a USB interface and a PCIe interface. The adaptive interface circuit includes a UAS protocol processing circuit, a data buffer, and an NVMe protocol processing circuit. The UAS protocol processing circuit receives a UAS command from a host via the USB interface and transmits a write-ready signal to the host according to the UAS command so that the host transmits host data to the data buffer according to the write-ready signal; the UAS protocol processing circuit also provides the UAS command to the NVMe protocol processing circuit. The NVMe protocol processing circuit generates X NVMe command(s) according to the UAS command; afterwards the NVMe protocol processing circuit starts transmitting X doorbell signal(s) to a storage device via the PCIe interface so as to let the storage device retrieve the host data from the data buffer according to the X NVMe command(s).