Adaptive Interrupt Control for Storage Devices
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Solution Overview
Problem
Conventional computer systems experience performance degradation due to the high number of interrupts generated by storage devices with improved input/output processing speeds, leading to increased overhead and potential soft lockup bugs, as the host must frequently stop and recover programs to process interrupts.
Innovation Solution
A computer system with adaptive interrupt control (AIC) that adjusts the number of interrupts generated by storage devices based on the number of delayed input/output operations, using a load watcher, decision maker, and interrupt controller to optimize interrupt generation and reduce processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If storage device processing speed is improved, then input/output processing speed is improved, but number of interrupts increases
Solution Approach 1:
The patent combines multiple interrupt handling functions into a unified interrupt handler that processes interrupts from multiple storage devices. This merging approach reduces the total number of interrupt processing operations by consolidating handling logic, thereby mitigating the increase in interrupt quantity that results from improved storage device processing speeds.
Solution Approach 2:
The interrupt handler is designed with multi-functionality to handle various types of interrupts (completion interrupts, error interrupts, notification interrupts) from different storage devices through a single unified mechanism. This universal approach allows the system to manage increased interrupt volume efficiently without requiring separate handling paths for each interrupt type or device.
2Productivity
If number of interrupts increases, then interrupt processing frequency increases, but system performance degrades
Solution Approach 1:
The patent implements dynamic interrupt handling where the interrupt handler adapts its behavior based on system conditions. The unified handler can dynamically adjust processing priorities, batch multiple interrupts when possible, and optimize handling strategies based on current system load and interrupt types, thereby maintaining high processing frequency without degrading overall system performance.
Solution Approach 2:
The system incorporates feedback mechanisms where the interrupt handler monitors system state and adjusts its processing approach accordingly. By providing feedback loops that track interrupt patterns and system performance, the handler can optimize its operations to maintain high productivity while preventing performance degradation through adaptive response to system conditions.
3Speed
If interrupt handling is performed frequently, then IO completion responsiveness is improved, but overhead increases
Solution Approach 1:
The unified interrupt handler implements periodic action by batching multiple interrupt processing operations together where possible. Instead of handling each interrupt immediately and separately, the handler can accumulate and process multiple interrupts in periodic batches, maintaining IO completion responsiveness while reducing the frequency of individual handling operations and thereby lowering processing overhead.
Solution Approach 2:
The interrupt handler maintains continuity of useful action by ensuring that interrupt processing is performed efficiently and without unnecessary interruptions to the main processing flow. The unified handler design allows for continuous processing of interrupt streams while minimizing the overhead associated with context switching and handler entry/exit, thereby maintaining responsiveness while reducing energy loss.
Data Source
AI summary
A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.