Adaptive IP Clock Gating for Same-Cycle Re-Enable at High Frequency
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Solution Overview
Problem
Existing clock gating techniques are impractical for electronic devices with varying delay times, as they do not allow for synchronized state element switching, leading to suboptimal power reduction in systems with multiple IP blocks and higher frequencies.
Innovation Solution
A multi-level clock gating architecture with adaptive clock gating and dynamic voltage and frequency scaling (DVFS) is implemented, using a hysteresis scheme and IP clock frequency control units to selectively enable or disable high-level clock gates based on frequency, ensuring power efficiency and performance by synchronizing clock enable signals across different levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional clock gating is applied to remove clock signals from state elements, then power consumption is reduced, but it becomes impractical for electronic devices with different delay times as state elements cannot be switched in a synchronized manner
Solution Approach 1:
The clock gating function is segmented into multiple hierarchical levels (root clock gate, mid-level clock gates, local clock gates) distributed across different IP blocks. Each level independently manages clock signals for its specific scope, allowing synchronized switching across the entire device while enabling power reduction at each segment. This segmentation resolves the contradiction by making the system adaptable to different delay times at various hierarchical levels while maintaining overall power efficiency.
2Use of energy by moving object
If clock gating is applied to IP blocks, then power consumption is reduced, but at higher frequencies not all clock gates can be re-enabled within the same cycle, reducing power savings
Solution Approach 1:
The clock gating system implements dynamic frequency control where the operating frequency of each IP block can be independently adjusted. When an IP block enters a low-power state, the system dynamically scales down its clock frequency rather than completely disabling the clock. This dynamic approach allows clock gates to be re-enabled within the same cycle even at higher frequencies, maintaining both power savings and performance by adapting the clock frequency to the actual operational needs of each IP block.
3Use of energy by moving object
If high-level clock gates are used to reduce power consumption, then power efficiency is improved, but delay times increase
Solution Approach 1:
The clock gating architecture segments the clock distribution into multiple hierarchical levels, placing clock gates close to the state elements they control (local clock gates) rather than using a single high-level clock gate. This segmentation reduces the delay time by minimizing the physical distance and number of logic levels between the clock gate and state elements, while still achieving power efficiency through the hierarchical structure that allows selective gating at each level.
Data Source
AI summary
Adaptive clock gating may provide improved power management of electronic devices. Clock gating may include removing a clock signal to state elements when those state elements are not being used, and the adaptive clock gating may provide improved clock gating for higher-level clock gates operating at increased frequencies. In an example, the adaptive clock gating may enable clock gating for higher-level clock gates within IP blocks that may be otherwise prevented from using clock gating due to timing requirements. The adaptive clock gating may be used to reduce power consumed by the clock distribution of IP blocks, thereby providing improved power efficiency. An adaptive clock gating circuit may include an IP clock frequency control unit with an adaptive clock gating logic circuit. The adaptive clock gating logic circuit may be used to selectively enable or disable high-level clock gates for the target IP based on a selected clock frequency.