Adaptive JTAG Interconnection for Server Component Coverage
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Solution Overview
Problem
Existing JTAG chain designs in server systems face challenges such as low component coverage, high hardware costs due to extensive wiring, and inability to automatically select optimal data transfer rates, making it difficult to connect multiple components adaptively and efficiently.
Innovation Solution
A server JTAG component adaptive interconnection system utilizing a programmable device to simulate JTAG timing, test channels, and form a JTAG interconnection chain by connecting TDO and TDI signals, perform pressure testing, and adjust data rates, eliminating the need for level converters and simplifying the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a JTAG chain connects PCH, CPU0, and CPU1 using level conversion chips, then level conversion is implemented, but the coverage is limited to only these components and cannot adaptively connect other JTAG components
Solution Approach 1:
The patent implements a universal JTAG chain architecture where the TDI and TDO signals can adaptively connect to any JTAG component in the system through a standardized interface. The JTAG master device can dynamically configure the signal routing to include PCH, CPU0, CPU1, and other components such as PCIe cards and back-planes, making the chain versatile and adaptable to different system configurations without requiring dedicated wiring for each component type.
Solution Approach 2:
The JTAG chain employs dynamic signal routing capabilities where the connection path of TDI and TDO signals can be reconfigured based on which components are present in the system. The master device can dynamically add or remove components from the JTAG chain during operation, allowing the chain to adapt to changing system configurations rather than being fixed at design time.
2Reliability
If multiple discrete level converters are used in the JTAG chain, then level conversion is achieved, but the hardware cost increases
Solution Approach 1:
The patent merges the level conversion functionality into the standardized JTAG interface design itself, eliminating the need for separate discrete level converter chips. The TDI and TDO signal paths are designed to inherently handle level conversion requirements through the standardized interface protocol, reducing the bill of materials and hardware cost while maintaining reliable level conversion capability across different components.
3Ease of operation
If the JTAG chain uses a daisy chain wiring design, then connection is achieved, but the PCB design requirement and wiring complexity increase
Solution Approach 1:
The patent establishes a universal TDI/TDO signal interface standard that can connect to any JTAG component through a consistent wiring pattern. Instead of requiring complex daisy-chain wiring where each component needs specific connection points, the standardized interface allows any component to be connected using the same signal routing approach, significantly simplifying PCB layout and wiring design while maintaining ease of component connectivity.
4Speed
If the JTAG chain operates at an excessively high rate, then data transfer speed is improved, but the chain cannot implement scan-through and test
Solution Approach 1:
The JTAG chain implements dynamic rate adaptation where the operating speed can be adjusted based on the specific test requirements and component capabilities. The system can operate at high rates for data transfer when needed, and automatically reduce to appropriate lower rates when scan-through and testing operations are required, ensuring both speed performance and test reliability are maintained through adaptive rate control.
Data Source
AI summary
A server Joint Test Action Group (JTAG) component adaptive interconnection system and method. The system includes a JTAG master device, a programmable device, and a plurality of JTAG components. The programmable device is configured to simulate JTAG timing according to a JTAG protocol and test JTAG channels of the JTAG components connected to the programmable device one by one. The programmable device connects in series a Test Data Output (TDO) signal of a previous JTAG component with a Test Data Input (TDI) signal of a next JTAG component in the programmable device, connects a TDI signal of a first JTAG component with a TDI signal of the JTAG master device, and connects a TDO signal of a last JTAG component with a TDO signal of the JTAG master device, so as to form a JTAG interconnection chain.