Adaptive Lane Mapping for SoC DDR Memory Compatibility
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Solution Overview
Problem
The challenge of achieving PHY compatibility between electronic devices on a circuit board is exacerbated by changes in PHY interfaces and varying device densities, leading to design complexities and increased costs due to the need for dedicated versions of System-on-Chip (SoC) for different DDR memory device densities.
Innovation Solution
The implementation of adaptive interface lane adaptor circuitry that uses SoC configuration software to map PHY byte lanes between a DDR memory controller interface on an SoC and an external DDR memory device, allowing compatibility with multiple device densities without disrupting speed or functionality, through lane selector and configuration circuitry that dynamically routes data lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dedicated version of SoC is produced for each different DDR memory device density, then compatibility with specific devices is improved, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent implements a universal SoC design that can interface with multiple DDR memory device densities (8-bit, 16-bit, 32-bit, 64-bit) through a single device. The memory controller includes reconfigurable data bus width and adaptive lane mapping capabilities, allowing the same SoC to adapt to different device requirements without requiring dedicated versions for each density.
Solution Approach 2:
The patent employs dynamic reconfiguration of the memory controller's data bus width and adaptive lane mapping that can be adjusted at runtime based on the connected memory device's density. The system can dynamically select which PHY byte lanes to activate and how to map them, enabling the same hardware to operate with different device configurations without physical changes.
2Adaptability or versatility
If a dedicated version of SoC is produced for each different DDR memory device density, then compatibility with specific devices is improved, but manufacturing costs increase
Solution Approach 1:
The patent implements a universal SoC design that can interface with multiple DDR memory device densities (8-bit, 16-bit, 32-bit, 64-bit) through a single device. The memory controller includes reconfigurable data bus width and adaptive lane mapping capabilities, allowing the same SoC to adapt to different device requirements without requiring dedicated versions for each density.
3Adaptability or versatility
If PHY interface changes are made to support new device versions, then functionality is improved, but compatibility with existing devices is lost
Solution Approach 1:
The patent employs dynamic reconfiguration of the memory controller's data bus width and adaptive lane mapping that can be adjusted at runtime based on the connected memory device's density. The system can dynamically select which PHY byte lanes to activate and how to map them, enabling the same hardware to operate with different device configurations without physical changes.
Solution Approach 2:
The patent changes operational parameters of the PHY interface, specifically the data bus width and lane mapping configuration, to accommodate different memory device densities. By adjusting these parameters rather than changing the physical interface structure, the system maintains compatibility across device versions while supporting new functionalities.
Data Source
AI summary
Systems, methods, and circuitries adapt a system-on-chip (SoC) for use with different external devices. In one example, an SOC includes a plurality of SoC data lanes configured to conduct data signals between the SoC and an external device interface. The SoC also includes an interface lane adaptor and a device interface including a plurality of interface connectors. The interface lane adaptor circuitry includes a plurality of SoC adaptor connectors connected to the interface connectors; a plurality of external adaptor connectors connected to the SoC data lanes and configured to be connected to the external device interface; a lane selector circuitry configured to connect a selected one of a first or a second SoC adaptor connector to a selected SoC data lane; and a lane configuration circuitry configured to control the lane selector circuitry to connect either the first or the second SoC adaptor connector to the selected SoC data lane.