Adaptive Last Level Cache Policy for Multicore SoC
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Solution Overview
Problem
Standard cache implementations, particularly those using the least recently used (LRU) replacement policy, are inefficient in handling high bandwidth networking systems with certain data traffic patterns, such as high rate streaming I/O and high rate random accesses, leading to increased DRAM bandwidth consumption and cache thrashing.
Innovation Solution
A dynamically adaptive last level cache population policy that uses a modified LRU scheme combined with an additional state bit in cache tags, allowing for profile-based allocation decisions that optimize cache allocation based on stream types and access patterns, thereby minimizing thrashing and improving hit rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard LRU replacement policy is used in last level cache, then cache allocation is simple and fast, but cache thrashing occurs and hit rates decrease for high bandwidth networking traffic patterns
Solution Approach 1:
The patent implements a dynamically adaptive cache allocation policy that transitions from static LRU to a flexible system using state bits and profiles. The cache controller dynamically selects allocation policies based on traffic pattern detection, adjusting behavior in real-time to match actual workload characteristics rather than relying on fixed replacement rules.
Solution Approach 2:
The patent introduces state bits in cache tags and profile parameters that modify cache allocation behavior. By changing the state parameters (state bit values and profile selections), the system adapts its allocation strategy to different traffic patterns, transforming the cache from a single-policy system to a multi-parameter controlled system.
2Productivity
If cache lines are allocated for L1 and L2 cache read-miss accesses in last level cache, then processor cache performance improves, but useful data in LLC is thrashed
Solution Approach 1:
The patent applies different allocation behaviors to different cache scenarios. Instead of a uniform allocation policy, the system uses local quality by applying specific allocation rules based on the type of access (read-miss vs. write-miss) and the detected traffic pattern, allowing optimized handling for each scenario rather than one-size-fits-all approach.
Solution Approach 2:
The patent performs preliminary action by detecting traffic patterns and selecting appropriate profiles before cache allocation decisions are made. The system proactively identifies the type of traffic and pre-selects the optimal allocation strategy, preventing thrashing before it occurs rather than reacting after damage is done.
3Loss of energy
If modified LRU scheme with state bits and profiles is implemented, then cache allocation optimizes for specific traffic patterns and reduces DRAM bandwidth consumption, but cache controller complexity increases
Solution Approach 1:
The patent segments the cache control logic into distinct components: traffic pattern detection module, profile selection module, state bit management, and allocation execution module. This segmentation allows each component to handle a specific aspect of the complex control task, making the overall system more manageable and implementable despite the increased functionality.
Data Source
AI summary
A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected profile from plural profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected profile for a selected least recently used (LRU) position in the cache.