Adaptive Set-Reset Latch Circuit for Fine Clock Stretching
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Solution Overview
Problem
Conventional clocking circuitry in modern circuit architectures lacks a small, energy and area efficient circuit that can provide clock stretching smaller than a factor of 2, which is essential for effective droop mitigation.
Innovation Solution
The implementation of a novel adaptive clocking architecture utilizing multiple latches and logic that allows for a reduced clock frequency with a 50% larger period, enabling an extra stretch step between nominal and half-frequency clock without using a delay locked loop (DLL).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional clocking circuitry uses traditional logic circuitry such as buffers and clock gates, then the circuit can provide basic clocking functions, but it cannot provide clock stretching smaller than a factor of 2 in an energy and area efficient manner
Solution Approach 1:
The patent segments the clocking function into multiple latches (first latch, second latch, third latch) that can be independently controlled. Each latch can be enabled or disabled based on droop detection, allowing fine-grained control of clock stretching in 50% steps rather than fixed factor-of-2 division. This segmentation enables adaptable clock stretching while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The patent implements dynamic clock stretching by using enable signals that can be selectively activated based on power supply droop detection. The clocking circuit transitions from static fixed-frequency operation to dynamic adaptive operation, where the clock period can be extended by 50% increments when droop is detected, allowing the system to adapt clock frequency in real-time without requiring complex reconfiguration.
2Adaptability or versatility
If a delay locked loop (DLL) is used for clock stretching, then the circuit can provide frequency multiplication and division, but it increases power consumption and area usage
Solution Approach 1:
The patent extracts the essential frequency control function from the complex DLL architecture and implements it using simple latches and enable signals. By removing the DLL's phase detection, feedback control, and frequency synthesis components, the design retains only the core functionality of frequency division and stretching, achieving the same adaptability with dramatically reduced power consumption and area.
Solution Approach 2:
The patent replaces the expensive, complex DLL with inexpensive latch-based circuitry that achieves comparable frequency control. The simple latch structure requires minimal power and occupies small area, providing a cost-effective alternative that delivers the necessary frequency stretching capability without the overhead of a full DLL implementation.
3Productivity
If the clock frequency is reduced to mitigate power supply droop, then the average CPU performance is improved, but the clock period increases
Solution Approach 1:
The patent applies partial clock stretching by extending the clock period by exactly 50% when droop is detected, rather than applying full factor-of-2 division. This partial action provides sufficient mitigation for power supply droop while minimizing the impact on CPU performance. The enable signals activate only the necessary latches to achieve the required period extension, avoiding excessive clock stretching that would unnecessarily reduce productivity.
Data Source
AI summary
In one implementation, a device includes a set-reset architecture with multiple latches including a first latch, a second latch and a third latch. The first latch may receive a first data signal from first logic and provide a first latched data signal as a first output based on a clock signal. The second latch may receive a second data signal from second logic and provide a second latched data signal as a second output based on the clock signal. The third latch may receive a third data signal from third logic and provide a third latched data signal as a third output based on the clock signal.