Adaptive Latch Feedback Filter for Single Event Upset Rejection
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Solution Overview
Problem
Conventional methods for mitigating single event upsets (SEUs) in digital circuits, such as increasing inertial delay or using delay lines, result in larger circuit sizes, slower speeds, and fixed immunity to radiation, which are inflexible and inefficient.
Innovation Solution
A novel transient filter is placed within the feedback loop of each latch, comprising a controllable inertial delay inverter and an inverter, with controllers to precisely control rise and fall times, allowing adaptive rejection of pulses less than the longest anticipated transient duration, independent of process variations or conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods increase inertial delay or use delay lines to mitigate SEU, then SEU resistance is improved, but circuit size increases and speed decreases
Solution Approach 1:
The patent implements dynamic control of inertial delay by introducing controllable delay elements that can adjust their delay characteristics based on operational conditions. The system transitions from fixed delay lines to dynamically adjustable delay mechanisms, allowing optimization of both SEU resistance and circuit speed through real-time parameter adjustment.
Solution Approach 2:
The invention changes the parameter of inertial delay from a fixed value to a controllable variable. By using controllable delay elements with adjustable delay times, the system can optimize the balance between SEU mitigation and performance, avoiding the need for excessively large fixed delay margins.
2Reliability
If conventional methods increase inertial delay or use delay lines to mitigate SEU, then SEU resistance is improved, but circuit size increases
Solution Approach 1:
The patent replaces static delay lines with dynamic controllable delay elements that achieve the same SEU mitigation effect with reduced area. The dynamic nature allows the circuit to achieve adequate inertial delay without requiring the excessive area margins needed by conventional fixed approaches.
Solution Approach 2:
By making the delay parameter controllable rather than fixed, the system can achieve adequate SEU resistance with optimized area utilization. The controllable delay elements provide the necessary pulse rejection capability without requiring the oversized fixed delay structures of conventional designs.
3Reliability
If fixed delay values are used to accommodate worst-case variations, then SEU resistance is improved, but performance penalty increases
Solution Approach 1:
The patent implements dynamic adjustment of delay parameters to match actual operating conditions rather than using fixed worst-case values. This allows the system to maintain adequate SEU resistance while avoiding the excessive performance penalty imposed by conservative fixed delay design.
Solution Approach 2:
The invention changes delay parameters from fixed worst-case values to dynamically adjustable values that adapt to actual process variations and operating conditions. This optimization eliminates unnecessary performance degradation while maintaining adequate SEU mitigation.
4Reliability
If larger delay margins are used to control transient filtering, then SEU resistance is improved, but circuit speed decreases by factor of two or more
Solution Approach 1:
The patent implements dynamic control of delay margins to provide adequate transient filtering only when needed, rather than using excessively large fixed margins. This allows the circuit to maintain high speed operation while achieving the necessary pulse rejection capability for SEU mitigation.
Data Source
AI summary
A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.