Adaptive Latency Scheduling for Event-Based Processors

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Solution Overview

Problem

Current event-based processing systems suffer from processing lag due to throttling, which results in high latency for latency-sensitive event-based processors, leading to potential loss of functionality as events are delayed, especially during high event loads.

Innovation Solution

Implement a dynamic prioritization system that monitors latency-sensitive event-based processors, allowing them to process more events at a higher frequency when latency exceeds predefined thresholds, and reverting to normal processing when latency returns to acceptable levels to conserve system resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If throttling is applied to constrain the number of events processed by each event-based processor, then system resource allocation is improved, but processing latency increases for latency-sensitive processors

Engineering Contradiction:
Improvesystem resource allocationVSAvoidprocessing latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system dynamically adjusts the number of events that can be processed by each event-based processor based on real-time latency measurements. The constraint on the number of events is not fixed but varies according to whether the processor is latency-sensitive and currently experiencing high latency, allowing the system to optimize between resource allocation and processing speed adaptively

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different event-based processors are treated differently based on their latency sensitivity and current performance state. Latency-sensitive processors experiencing high latency receive relaxed constraints and higher processing priority, while non-latency-sensitive or well-performing processors maintain standard constraints, creating localized optimization rather than uniform treatment

Inventive Principle:
Principle #3Local quality

2Device complexity

If all event-based processors are given equal priority in processing events, then system simplicity is maintained, but latency-sensitive processors experience processing lag during high event loads

Engineering Contradiction:
Improveprocessor scheduling simplicityVSAvoidfunctionality reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system continuously measures latency for latency-sensitive event-based processors and uses this feedback to dynamically adjust processing priorities and constraints. When latency exceeds thresholds, the system responds by relaxing event processing constraints and increasing priority, creating a closed-loop control mechanism that maintains functionality reliability

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Processor priority and event processing constraints are not static but dynamically adjusted based on real-time latency conditions. The system transitions from equal priority treatment to differentiated priority levels when latency-sensitive processors are detected to be experiencing delays, maintaining simplicity while improving reliability through dynamic adaptation

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11334389B2Adaptive scheduling of latency-sensitive event-based processors
Publication Date: 2022.05.17 MICROSOFT TECHNOLOGY LICENSING LLC
  • US11334389B2 patent drawing
  • US11334389B2 patent drawing
  • US11334389B2 patent drawing

AI summary

The latency corresponding to a latency-sensitive event-based processor is evaluated to determine whether the latency-sensitive event-based processor (EBP) should be prioritized. If so, constraints on the number of events that the latency-sensitive EBP can process are relaxed and the frequency with which the latency-sensitive EBP can process events is increased. At a next latency evaluation, if the latency-sensitive EBP no longer meets criteria for prioritization, the constraint on the number of events is returned to a nominal level, as is the frequency with which the latency-sensitive EBP can process events.