Adaptive Latency Tolerance for Memory Bus Power Management

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Solution Overview

Problem

In memory systems, particularly in mobile devices, there is a challenge in balancing power consumption and latency in bus interfaces like PCIe, as they consume high power in low latency states, which affects battery life and performance.

Innovation Solution

The storage device assesses the power supply state and selects a latency tolerance for the bus interface, indicating it to the host, which then applies this tolerance to adaptively manage power consumption by selecting appropriate power-saving states, data rates, and clock gating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the bus interface operates in low latency states, then data transfer performance is improved, but power consumption increases

Engineering Contradiction:
Improvedata transfer speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic adaptation of latency tolerance based on real-time power supply state assessment. The storage device continuously monitors power availability and adjusts the bus interface latency tolerance accordingly, transitioning between performance and power-saving modes dynamically rather than using fixed settings

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the latency tolerance parameter of the bus interface based on power supply conditions. When power is available, the system uses lower latency tolerance for optimal performance. When power is constrained, the system increases latency tolerance to reduce power consumption, directly manipulating the key parameter to resolve the contradiction

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If power-saving states are selected, then power consumption is reduced, but latency increases

Engineering Contradiction:
Improvepower consumptionVSAvoidlatency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the storage device assesses the power supply state and uses this information to determine appropriate latency tolerance levels. This closed-loop feedback allows the system to automatically adjust latency settings based on actual power conditions, balancing power savings with performance requirements

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts latency tolerance based on real-time power availability. The latency setting is not fixed but adapts continuously according to power supply state, allowing the system to optimize between power consumption and latency based on current operational conditions

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If battery energy level is low, then power consumption should be reduced, but performance deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem performance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent changes the latency tolerance parameter in response to battery energy level. When energy is low, the system increases latency tolerance to enable power-saving states, thereby reducing power consumption. This parameter adjustment directly addresses the contradiction between maintaining performance and conserving energy

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The storage device autonomously assesses power supply state and determines appropriate latency tolerance without external intervention. The system self-regulates by monitoring battery levels and automatically adjusting operational parameters to balance performance and power consumption based on available energy

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9229525B2Adaptive latency tolerance for power management of memory bus interfaces
Publication Date: 2016.01.05 APPLE INC
  • US9229525B2 patent drawing
  • US9229525B2 patent drawing

AI summary

A method includes, in a memory system that includes a host and a storage device connected by a bus interface, assessing in the storage device a power supply state of the memory system. In the storage device a latency tolerance is selected for the bus interface based on the assessed power supply state. The selected latency tolerance is indicated from the storage device to the host, for application to the bus interface.