Adaptive-Biased LDO Circuit for Wide Input Voltage Range
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Solution Overview
Problem
LDO circuits face challenges when employed in wide range input applications, particularly in systems requiring a wide operation voltage range and high-performance circuits like system-on-chip (SOC) digital circuits and computer processing units (CPUs), due to limitations in input range and incompatible manufacturing processes with traditional I/O transistors.
Innovation Solution
The use of core transistors with smaller channel lengths and strong driving capability, integrated into a power stage with adaptive biasing to protect against high-voltage stress, combined with a cascode operational amplifier and feedback circuit to stabilize output voltage and minimize noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional I/O transistors are used in LDO circuits, then the manufacturing process is compatible with standard processes, but the input voltage range is limited and the driving capability is insufficient
Solution Approach 1:
The patent changes the channel length parameter of the power transistor from traditional I/O transistor dimensions to core transistor dimensions (smaller channel length). This parameter change enables the LDO circuit to operate with a wider input voltage range and provides stronger driving capability, while the manufacturing process remains compatible with advanced semiconductor fabrication processes used for high-performance circuits
2Power
If core transistors with smaller channel lengths are used, then the driving capability and input range are improved, but the transistor becomes more susceptible to high-voltage stress
Solution Approach 1:
The patent introduces an adaptive biasing circuit as an intermediary mechanism that dynamically adjusts the gate-source voltage of the core transistor. This biasing circuit acts as a mediator that protects the small-channel-length transistor from high-voltage stress by controlling its operating point, while still allowing the transistor to provide strong driving capability when needed
Solution Approach 2:
The patent implements dynamic biasing where the gate-source voltage of the power transistor is not fixed but adapts in response to input voltage conditions. This dynamic adjustment allows the transistor to operate optimally across different voltage ranges while being protected from excessive stress conditions
3Adaptability or versatility
If the LDO circuit is designed for wide input range operation, then the adaptability is improved, but the stability and noise performance may deteriorate
Solution Approach 1:
The patent employs a feedback mechanism through the operational amplifier that continuously monitors the output voltage and adjusts the power transistor's gate voltage accordingly. This feedback control maintains output voltage stability even when the input voltage varies across a wide range, preventing the deterioration of performance that would otherwise occur in wide-range operation
Data Source
AI summary
The present disclosure provides a low drop-out (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.