Adaptive LDPC Decoder Modes for Lower-Power ECC Correction

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Solution Overview

Problem

Existing error correction code (ECC) circuits in storage devices face challenges in efficiently managing power consumption and error correction capabilities during multiple stages of ECC decoding, particularly when initial decoding fails.

Innovation Solution

The implementation of an LDPC decoder that variably sets operation modes for each column based on column degree and error level, allowing for ultra-low-power, low-power, and normal decoding modes, reducing power consumption while maintaining or enhancing error correction capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC decoding is repeatedly performed in multiple stages to increase reliability and correction capability, then error correction capability is improved, but power consumption increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the decoding operation mode adjustable and changeable based on conditions. The LDPC decoder can dynamically switch between different operation modes (first, second, third modes) depending on the column degree and error level, rather than using a fixed decoding approach. This dynamic adaptation allows the system to optimize power consumption while maintaining error correction capability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes operational parameters (operation mode, message size between check nodes and variable nodes) based on column degree and error level. By varying these parameters adaptively during the decoding process, the system can reduce power consumption in certain columns while maintaining overall error correction performance through parameter optimization.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If uniform high-capability decoding is applied to all columns, then error correction capability is improved, but power consumption increases unnecessarily

Engineering Contradiction:
Improveerror correction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by treating different columns differently based on their specific characteristics (column degree). Instead of applying uniform decoding to all columns, the system determines operation modes locally for each column based on its error level and column degree, allowing optimized power consumption for each column while maintaining overall error correction capability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the decoding process into different operation modes (first, second, third modes) that can be applied to different columns based on their characteristics. This segmentation allows the system to apply appropriate decoding strength to each column, avoiding unnecessary power consumption in columns that don't require high-capability decoding.

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If adaptive operation modes are set for each column based on column degree and error level, then power consumption is reduced, but decoding complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoiddecoding complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent manages decoding complexity by systematically changing parameters (operation mode, message size) based on measurable characteristics (column degree, error level). This parameter-based approach provides a structured method for adaptive decoding that balances power consumption reduction with manageable complexity through clear decision rules.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4456436B1Error correction code (ECC) circuit including low-density parity-check decoder in adaptive operation mode, operating method of the ECC circuit, and memory controller including the ECC circuit
Publication Date: 2025.12.24 SAMSUNG ELECTRONICS CO LTD
  • EP4456436B1 patent drawingFigure 1
  • EP4456436B1 patent drawingFigure 2
  • EP4456436B1 patent drawingFigure 3A

AI summary

An example operating method of an error correction code (ECC) circuit includes receiving a codeword from a memory device, calculating a syndrome vector based on the codeword and a parity-check matrix indicating whether messages are exchanged between check nodes and variable nodes, performing, when the syndrome vector is not a zero vector, sequential decoding on a plurality of columns of the parity-check matrix by decoding a first column in a first operation mode, the first column having a first variable node degree, decoding a second column in a second operation mode, the second column having a second variable node degree, and decoding a third column in a third operation mode, the third column having a third variable node degree, and calculating the syndrome vector whenever the sequential decoding of the plurality of columns is completed and iteratively performing the sequential decoding until the syndrome vector is the zero vector.