Adaptive LDPC Interleaver Layout for Modulation Symbol Mapping

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Solution Overview

Problem

Current communication systems face challenges in overcoming noise, fading, and inter-symbol interference, particularly in high data throughput applications like next-generation mobile communication and digital broadcasting, where existing error-correction codes are complex and inefficient.

Innovation Solution

A transmitting apparatus and method that employs a Low Density Parity Check (LDPC) code encoder, interleaver, and modulator to map LDPC codeword bits onto modulation symbols using a block interleaver with specific row configurations based on modulation methods, enhancing encoding and reception performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional error-correction codes are used in high data throughput applications, then data transmission can be achieved, but encoding complexity increases and decoding efficiency decreases

Engineering Contradiction:
Improvedata throughputVSAvoidencoding complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The LDPC codeword is divided into multiple bit groups, with each group containing a specific number of bits. This segmentation allows the interleaver to process and organize bits in manageable units, reducing the overall encoding complexity while maintaining high data throughput capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic row configuration in the block interleaver where the number of rows in the first part is determined differently depending on the modulation method, and the number of rows in the second part is determined based on the first part. This dynamic adaptation optimizes encoding efficiency for different modulation schemes without requiring separate encoders for each method

Inventive Principle:
Principle #15Dynamics

2Reliability

If LDPC codes are used to overcome noise and interference, then reception reliability improves, but the mapping complexity onto high order modulation bits increases

Engineering Contradiction:
Improvereception reliabilityVSAvoidmapping complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The block interleaver is divided into a first part and a second part with different row configurations. The first part handles bit groups writable in bit group units with a specific number of rows determined by the modulation method, while the second part handles remaining bits with rows determined based on the first part. This local differentiation simplifies the mapping process for each section while maintaining overall reliability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the interleaver structure parameters (number of rows in first and second parts) based on the modulation method being used. This parameter adaptation allows the same LDPC encoder to efficiently map codewords onto different high-order modulation schemes without increasing mapping complexity

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If block interleaver with fixed row configuration is used, then implementation is simplified, but encoding performance deteriorates for different modulation methods

Engineering Contradiction:
Improveimplementation simplicityVSAvoidencoding performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The block interleaver uses dynamic row configuration where the number of rows in the first part is determined differently depending on the modulation method, and the number of rows in the second part is determined based on the first part. This dynamic structure maintains implementation simplicity while adapting to different modulation methods to preserve encoding performance

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10355714B2Transmitting apparatus and signal processing method thereof
Publication Date: 2019.07.16 SAMSUNG ELECTRONICS CO LTD
  • US10355714B2 patent drawing
  • US10355714B2 patent drawing
  • US10355714B2 patent drawing

AI summary

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.