Adaptive Leading Edge Blanking Circuit for Switch Control
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Solution Overview
Problem
Existing integrated control circuits for switching converters face issues with spurious signals on the leading edge of the current signal causing false activations and premature conduction end of power transistors, which can lead to irregular converter operation due to parasitic capacitance discharge and reverse recovery of rectifier diodes, and existing leading edge blanking circuits have limitations in frequency range and effectiveness.
Innovation Solution
An integrated circuit with a blanking device that compares a current signal with a voltage error signal, generates a driving signal for a power transistor, and selectively masks the signal for a first and second time period based on the detection of spikes on the leading edge, with the first period determined by the turn-on delay and the second period by the spike duration, allowing for adaptive blanking to suppress leading edge spikes effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed blanking period is used to suppress leading edge spikes, then spike suppression is achieved, but the blanking period cannot be optimized for different spike durations and turn-on delays
Solution Approach 1:
The patent applies dynamics by making the blanking period variable rather than fixed. The blanking period adapts based on the actual turn-on delay of the power transistor and the duration of the leading edge spike, allowing the circuit to optimize spike suppression for each switching cycle according to real-time conditions.
Solution Approach 2:
The patent changes the parameter of blanking period duration dynamically. The blanking period is adjusted as a function of the power transistor's turn-on delay and the measured spike duration, enabling the circuit to adapt to varying operating conditions and achieve optimal suppression effectiveness.
2Reliability
If the blanking period is extended to ensure complete spike suppression, then reliability improves, but the minimum on-time of the power transistor increases
Solution Approach 1:
The patent uses dynamics to adjust the blanking period length based on actual spike characteristics. By measuring the turn-on delay and spike duration in real-time, the blanking period is extended only as much as necessary to suppress the spike, avoiding unnecessary extension that would increase the minimum on-time.
Solution Approach 2:
The patent applies partial action by providing just enough blanking period to suppress the spike effectively, rather than using a fixed excessive blanking period. The blanking duration is tailored to match the actual spike duration plus turn-on delay, avoiding over-blanking that would unnecessarily extend the minimum on-time.
3Reliability
If leading edge blanking is applied to suppress spikes, then false activations are reduced, but the circuit complexity increases
Solution Approach 1:
The patent applies self-service by using the power transistor's own turn-on delay and the spike characteristics to determine the blanking period duration. The circuit measures the actual turn-on delay and spike duration, then uses these measurements to automatically set the appropriate blanking period, eliminating the need for external adjustment components.
Solution Approach 2:
The patent uses feedback by measuring the turn-on delay and spike duration, then using these measurements to adjust the blanking period. The circuit continuously monitors the switching behavior and adapts the blanking duration accordingly, creating a closed-loop system that optimizes spike suppression while minimizing impact on minimum on-time.
Data Source
AI summary
An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal.