Adaptive Leading Edge Blanking Time for Current-Mode SMPS

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Solution Overview

Problem

Current-mode switch-mode power supplies face challenges in filtering out leading edge current peaks caused by inherent or stray capacitance, which can lead to premature switching off of power transistors due to excessive detected current, necessitating effective leading edge blanking time generation to prevent incorrect control actions.

Innovation Solution

A current-mode switch-mode power supply controller with a switch controller, falling edge detector, and leading edge blanking time logic that asserts the leading edge blanking signal when the gate signal is asserted and ends it upon detection of a falling edge in the current sense signal, ensuring the primary switch remains on during the leading edge blanking time, thereby filtering out current spikes and preventing premature switching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a current or resistor is used to charge a capacitor to generate LEB time, then the LEB time can be generated, but the LEB time may not accurately match the real peak current time due to fixed delay

Engineering Contradiction:
ImproveLEB time accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the LEB time variable rather than fixed. The LEB time is dynamically adjusted based on the actual current sense signal characteristics - specifically, the LEB period ends when the current sense signal falls below a threshold, allowing the blanking time to adapt to different operating conditions and accurately match the real peak current duration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses feedback by continuously monitoring the current sense signal during the LEB period. The falling edge detector monitors the current sense signal and provides feedback to end the LEB time when the signal returns to normal levels, creating a closed-loop system that automatically adjusts the blanking duration based on actual circuit conditions.

Inventive Principle:
Principle #23Feedback

2Reliability

If LEB time is extended to filter out leading edge current peaks, then premature switching is prevented, but the response time to detect actual current conditions is delayed

Engineering Contradiction:
Improveswitching control accuracyVSAvoidcurrent detection delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The LEB time is dynamically adjusted based on actual current conditions rather than using a fixed extended delay. The blanking period automatically shortens when the current sense signal falls below the threshold, reducing unnecessary time loss while maintaining reliability during actual peak conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Instead of using a fixed excessive LEB time that always extends beyond the actual peak, the patent applies partial action by ending the LEB time as soon as the current sense signal returns to normal levels. This provides just enough blanking to filter peaks without excessive delay, optimizing both reliability and response time.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9654014B1Adaptive leading edge blanking time generation for current-mode switch-mode power supplies
Publication Date: 2017.05.16 INFINEON TECH AUSTRIA AG
  • US9654014B1 patent drawing
  • US9654014B1 patent drawing
  • US9654014B1 patent drawing

AI summary

A current-mode switch-mode power supply controller includes a switch controller, a falling edge detector, and leading edge blanking (LEB) time logic. The switch controller is arranged to control regulation of an output signal via current-mode regulation by turning a primary switch on and off based on a current sense (CS) signal and an LEB signal, such that the switch controller is arranged to cause the primary switch to remain on while the LEB time signal is asserted. The falling edge detector is arranged to detect a falling edge in the CS signal. The LEB time logic is arranged to provide the LEB time signal such that the assertion of the LEB time signal begins when a gate signal is asserted, and such that the assertion of the LEB time signal ends when the falling edge detector detects the falling edge in the CS signal.