Load/Store Chunk Instructions for Adaptive Memory Copies
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Solution Overview
Problem
Existing data processing systems face inefficiencies in implementing memory copy and comparison functions, such as memcpy(), due to varying micro-architectural dependencies and the need for iterative loops, leading to performance variability and suboptimal execution across different platforms.
Innovation Solution
Implementing load and store chunk instructions that determine the number of bytes to load or store based on implementation-specific conditions, allowing flexibility in handling memory operations and supporting interruptible sequences, while considering alignment and resource availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If iterative loops are used to implement memory copy functions, then compatibility across different platforms is improved, but execution performance deteriorates due to repeated branch predictions and loop overhead
Solution Approach 1:
The patent segments the memory copy operation into fixed-size chunks (e.g., 16-byte or 32-byte blocks) that can be processed by vector instructions. Instead of copying byte-by-byte through iterative loops, the processor divides the source and destination memory regions into multiple chunks and processes each chunk in parallel using vector load and store instructions, eliminating loop overhead while maintaining platform compatibility through standardized vector operation semantics.
Solution Approach 2:
The patent replaces the mechanical iterative loop structure with hardware-level vector instructions that perform bulk memory operations in a single instruction cycle. The vector load instruction loads multiple data elements simultaneously into vector registers, and the vector store instruction stores them back to memory without requiring iterative loop control, branch prediction, or multiple sequential instructions, thereby substituting the software-controlled mechanical loop with a hardware-optimized vector operation.
2Device complexity
If fixed chunk size is used for memory operations, then instruction simplicity is improved, but adaptability to different micro-architectural constraints deteriorates
Solution Approach 1:
The patent introduces dynamic chunk sizing capability where the processor can adjust the size of memory chunks based on micro-architectural conditions such as cache line size, vector register width, and memory alignment requirements. The vector load and store instructions support variable-length operations that adapt to different micro-architectures while maintaining a simple unified instruction format, allowing the same instruction to efficiently operate with different chunk sizes on different processor platforms.
Solution Approach 2:
The patent enables parameter changes in the vector memory operations by allowing the chunk size to be modified based on implementation-specific conditions. The instruction decoder and execution units can adjust operational parameters such as the number of bytes to load or store in a single vector operation, enabling the same instruction set to adapt to different micro-architectural constraints including varying cache hierarchies, memory bandwidths, and alignment requirements without requiring platform-specific instruction variations.
3Productivity
If vector registers are used to store chunk data, then memory operation efficiency is improved, but register resource consumption increases
Solution Approach 1:
The patent segments the data processing into multiple vector register operations, where each vector register holds a portion of the chunk data. Instead of requiring a single large register to hold all data, the total data is divided into smaller segments that fit within available vector register widths (e.g., 128-bit, 256-bit, or 512-bit registers). This segmentation allows efficient utilization of available register resources while maintaining high memory operation throughput through parallel vector processing.
Solution Approach 2:
The patent ensures continuity of useful action by implementing a pipeline architecture where vector load, compute, and store operations can overlap and proceed concurrently. While one vector register is being loaded from memory, another is being processed, and a third is being stored back, maximizing the utilization of vector register resources without idle cycles. This continuous operation maintains high memory efficiency while managing register allocation through overlapping execution stages.
Data Source
AI summary
Processing circuitry (16) and an instruction decoder (9) supports a load chunk instruction and a store chunk instruction which can be useful for implementing memory copy functions and other library functions for manipulating or comparing blocks of memory. Number of bytes to load or store in response to these instructions is determined based on an implementation specific condition. As well as loading or storing bytes of data, the load chunk instruction and (10) store chunk instruction also designated a load/store length value as data corresponding to an architecturally visible register, which provides an indication of a number of bytes loaded or stored.