Adaptive LRU Memory Controller for NVDIMM Page Management
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Solution Overview
Problem
Current NVDIMM devices face inefficiencies in memory page management, leading to high management costs and inability to fully utilize the quick access features of DRAM, resulting in reduced operating efficiency.
Innovation Solution
A memory controller and page management method that includes an NVDIMM interface, SRAM, and a processor to manage DRAM and NVM pages by using adaptive LRU lists and FIFO lists to optimize data access and caching, determining cache hit states, and adjusting page mappings to minimize management resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NVDIMM device uses conventional memory page management, then data persistence is achieved, but management cost increases and operating efficiency decreases
Solution Approach 1:
The patent segments the memory management system into distinct components: a file system layer that handles high-level file operations, a translation layer that converts file operations to page operations, and a page cache layer that manages actual data storage. This segmentation allows each layer to be optimized independently, improving overall operating efficiency while maintaining data persistence through the NVDIMM hardware.
Solution Approach 2:
The patent introduces a translation layer as an intermediary between the file system and the page cache. This intermediary converts file operations into page operations, enabling efficient memory management without requiring the file system to directly manage individual pages. This reduces management overhead and improves operating efficiency while preserving data persistence.
2Reliability
If NVDIMM device uses conventional memory page management, then data persistence is achieved, but management cost increases
Solution Approach 1:
The patent extracts the complex page management functionality from the file system and implements it as a separate, dedicated page cache layer. This extraction simplifies the file system's responsibilities and reduces overall management complexity, while the specialized page cache layer efficiently handles persistence operations through the NVDIMM device.
Solution Approach 2:
The page cache layer implements self-service mechanisms by automatically managing page allocation, caching policies, and persistence operations without requiring complex external management. This self-service approach reduces management overhead and simplifies the overall system architecture while maintaining data persistence.
3Reliability
If NVDIMM device lacks optimized page management, then data persistence is maintained, but quick access feature of DRAM is not fully utilized
Solution Approach 1:
The patent implements a page cache that pre-loads and caches frequently accessed pages in the DRAM portion of the NVDIMM device. By performing preliminary actions to populate the cache with anticipated data, the system ensures that future accesses can be served from the fast DRAM memory, fully utilizing its quick access feature while maintaining persistence through the NVM backup.
Solution Approach 2:
The patent implements dynamic cache management that adapts to access patterns, automatically adjusting which pages are cached in DRAM versus stored in NVM. This dynamic allocation optimizes access speed by keeping frequently accessed data in fast memory while maintaining persistence, allowing the system to fully utilize DRAM's quick access features.
Data Source
AI summary
A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.