Adaptive Mapping Table Compaction in Multimode SSDs for Lower DRAM Use

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Solution Overview

Problem

Modern SSDs face challenges in efficiently managing different I/O block sizes, particularly for AI-oriented applications with large active data sets, leading to high DRAM usage and inefficiencies in data access.

Innovation Solution

Implementing a multimode SSD with optimized mapping tables that partition and compact data blocks into sub-tables, using techniques like garbage collection and unaligned write request caching to reduce DRAM overhead and enhance data access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the entire LBA-PBA FTL mapping table is kept in DRAM to ensure high-speed operation, then access speed is improved, but DRAM cost overhead increases

Engineering Contradiction:
Improveaccess speedVSAvoidDRAM cost overhead
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent divides the FTL mapping table into multiple segments: a hot data portion stored in DRAM for fast access and a cold data portion stored in NAND flash memory for cost efficiency. This segmentation allows the system to maintain high-speed access for frequently accessed mappings while reducing overall DRAM requirements by storing less frequently accessed mappings in cheaper non-volatile memory.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If one or multiple consecutive LBAs are mapped onto one PBA to reduce intra-SSD DRAM cost overhead, then DRAM usage is reduced, but the ability to serve applications with different I/O block sizes becomes limited

Engineering Contradiction:
ImproveDRAM usageVSAvoidability to serve different I/O block sizes
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic LBA block size configuration that allows the SSD to adapt to different I/O block size requirements. The system can dynamically adjust the mapping granularity and consolidate LBAs into PBAs based on the specific access patterns and block size requirements of different applications, thereby maintaining versatility while optimizing DRAM usage for each workload scenario.

Inventive Principle:
Principle #15Dynamics

3Productivity

If mapping tables are partitioned into sub-tables with optimized sub-table sizes during garbage collection, then garbage collection efficiency is improved, but mapping table complexity increases

Engineering Contradiction:
Improvegarbage collection efficiencyVSAvoidmapping table complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent partitions the mapping table into multiple sub-tables organized in a hierarchical structure with different granularities. This segmentation enables the garbage collection process to operate on smaller, more manageable sub-tables independently, improving collection efficiency by reducing the scope of operations required. The hierarchical organization also allows different garbage collection strategies to be applied to different sub-tables based on their specific characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements selective garbage collection that focuses only on the necessary sub-tables rather than processing the entire mapping table. By identifying and collecting garbage only in sub-tables that contain invalid entries, the system improves garbage collection efficiency while avoiding unnecessary processing of clean sub-tables, thereby managing complexity through targeted partial action.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250284630A1Multimode solid-state drive with adaptive address mapping table compaction
Publication Date: 2025.09.11 SCALEFLUX INC
  • US20250284630A1 patent drawing
  • US20250284630A1 patent drawing
  • US20250284630A1 patent drawing

AI summary

A method for optimizing sub-table usage in a multimode solid-state drive having a plurality of flash memory chips addressable via PBAs and a controller chip that utilizes a set of mapping tables to map LBAs to PBAs and wherein each mapping table is partitioned into a set of sub-tables. In one approach, sub-tables are optimized during a garbage collection (GC) that includes: selecting a group of memory blocks and identifying valid LBAs of still-valid data in the memory blocks; sorting the valid LBAs to identify groups of consecutive LBAs; storing data associated with each group of consecutive LBAs to an associated group of consecutive PBAs during a GC copy operation; updating associated sub-tables, wherein only a first PBA of each group of consecutive PBAs is stored in the associated sub-table; and updating a metadata block for each associated sub-table to identify un-stored PBAs in the associated sub-table.