Adaptive Memory Address Translation Using Gray Code Encoding
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Solution Overview
Problem
In high bandwidth and low voltage systems, the condition where the page address is not hit but the bank address is hit leads to decreased system performance due to inefficient memory access and incorrect memory address translation, causing significant changes in current and reduced translation speed between logic 1 and logic 0.
Innovation Solution
An adaptive memory address translation method and memory controller that translates and codes memory addresses to reduce the difference between bank addresses for adjacent request instructions, utilizing a numerical translation mechanism to minimize bit differences and ensure the bank address is not hit, thereby allowing pipeline processing and reducing system performance loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory addresses are accessed using conventional addressing methods, then the memory can be accessed, but the system performance decreases when page address is not hit but bank address is hit
Solution Approach 1:
The patent applies parameter changes by translating memory addresses using Gray code encoding, which changes only one bit between adjacent addresses. This transformation modifies the address representation parameter to prevent the specific condition of page address miss combined with bank address hit, thereby eliminating the performance degradation without requiring architectural changes to the memory system.
2Speed
If memory addresses are translated using conventional methods, then address translation is performed, but translation speed decreases when multiple bits change simultaneously
Solution Approach 1:
The patent changes the parameter of address encoding from conventional binary to Gray code, ensuring that only one bit changes between adjacent memory addresses. This parameter transformation maintains translation speed by reducing the number of bit transitions while improving reliability by preventing incorrect address sampling that occurs when multiple bits change simultaneously in conventional binary encoding.
3Productivity
If memory operates at higher working speeds, then bandwidth increases, but current changes significantly when multiple address bits change
Solution Approach 1:
The patent applies parameter changes by encoding memory addresses in Gray code, which ensures that only one bit transitions between adjacent addresses. This reduces the instantaneous current consumption that occurs when multiple address bits change simultaneously, enabling the memory system to operate at higher speeds and achieve greater bandwidth without excessive energy consumption or signal integrity issues.
Data Source
AI summary
An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.