Adaptive Memory Clock Gating for Low-Power Synchronized Access
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Solution Overview
Problem
Current memory clock signal generation in computer systems leads to unnecessary power consumption and reduced data access efficiency due to continuous transmission of memory clock signals during non-data access periods, as well as the need for re-synchronization upon resuming data access.
Innovation Solution
A method and circuit for generating a gated memory clock signal that adapts its frequency based on the clock enable signal, using a clock generator, delay circuit, and gating circuit to produce a signal with reduced frequency during non-data access periods while maintaining synchronization, thus reducing power consumption without affecting data access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory clock signal is continuously transmitted during non-data access periods, then the system maintains readiness for immediate data access, but power consumption increases unnecessarily
Solution Approach 1:
The patent applies periodic action by generating the memory clock signal only during data access periods rather than continuously. The clock signal is enabled when data access is detected and disabled during non-access periods, creating a periodic on-demand clock generation pattern that reduces power consumption while maintaining system readiness.
Solution Approach 2:
The patent implements preliminary action by detecting data access requests in advance and enabling the clock signal before actual data transfer begins. This ensures the memory system is synchronized and ready for immediate operation when data access is required, eliminating the need for re-synchronization.
2Use of energy by moving object
If the memory clock signal frequency is reduced during non-data access periods, then power consumption decreases, but re-synchronization is required upon resuming data access
Solution Approach 1:
The patent uses feedback by continuously monitoring the data access state and dynamically adjusting the clock signal generation accordingly. When data access is detected, the system immediately restores the clock signal to its original frequency, using the feedback from access detection to trigger clock restoration without requiring re-synchronization sequences.
Solution Approach 2:
The system maintains preliminary synchronization state by preserving the phase relationship during clock suppression. When the clock signal is re-enabled, the memory system resumes operation from its last synchronized state rather than requiring full re-synchronization, effectively using preliminary action to avoid time loss.
3Use of energy by moving object
If the memory clock signal is completely disabled during non-data access periods, then power consumption is minimized, but data access efficiency is reduced due to re-synchronization requirements
Solution Approach 1:
The patent applies dynamics by making the clock signal generation adaptive and dynamic rather than static. The clock frequency and enable state change dynamically based on real-time data access conditions, allowing the system to optimize between power consumption and access efficiency by adjusting clock parameters according to actual operational needs.
Solution Approach 2:
The system implements parameter changes by modifying the clock signal parameters (frequency and enable state) based on data access conditions. When data access occurs, the clock signal parameters are changed from disabled or reduced-frequency state back to full-frequency enabled state, optimizing both power consumption and access efficiency through parameter adaptation.
Data Source
AI summary
A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.