Adaptive Memory Error Correction Using Syndrome-Guided Decoder Switching

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Solution Overview

Problem

Existing error correction algorithms in memory devices either require low hardware resources with limited error correction capabilities or high hardware resources with high error correction capabilities, making it challenging to select an appropriate algorithm for efficient data correction.

Innovation Solution

A memory device with a first and second error correction decoder, where the first decoder performs an initial error correction operation and calculates syndrome values to generate a control signal, determining whether to activate the second decoder with higher error correction capabilities based on the syndrome values, allowing adaptive adjustment of the error correction algorithm.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a low hardware resource error correction algorithm is used, then hardware resource consumption is reduced, but error correction capability deteriorates

Engineering Contradiction:

Improvehardware resource consumptionVSAvoiderror correction capability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent implements dynamic error correction capability adjustment by monitoring the number of error bits in data chunks and adaptively selecting between first and second error correction algorithms. The error correction capability is dynamically changed based on the actual error condition, allowing the system to use low hardware resource algorithms when errors are few and high capability algorithms when errors are numerous, thus resolving the contradiction between hardware resource consumption and error correction capability.

Inventive Principle:

Principle #15Dynamics

2Reliability

If a high hardware resource error correction algorithm is used, then error correction capability is improved, but hardware resource consumption increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidhardware resource consumption

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The system dynamically adjusts error correction capability by monitoring error bit counts and adaptively selecting between different error correction algorithms. When the number of error bits is small, the system uses the first error correction algorithm with lower hardware resource consumption. When the number of error bits exceeds a threshold, it switches to the second error correction algorithm with higher capability, thus avoiding unnecessary hardware resource consumption while maintaining adequate error correction capability.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the error correction algorithm parameter based on the error condition. By monitoring the number of error bits and comparing it with a preset threshold, the system selects different error correction algorithms (first algorithm for low error counts, second algorithm for high error counts), thereby optimizing the balance between error correction capability and hardware resource consumption according to actual needs.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If error correction algorithm is fixed, then device complexity is reduced, but adaptability to different error conditions deteriorates

Engineering Contradiction:

Improveerror correction system complexityVSAvoidadaptability to different error conditions

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic error correction algorithm selection by monitoring the number of error bits in data chunks. The system includes a first error correction decoder and a second error correction decoder, with a control mechanism that dynamically selects which decoder to activate based on the error condition. This dynamic approach enhances adaptability to different error conditions while maintaining relatively simple device complexity through modular decoder design and conditional activation.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the error correction algorithm parameter based on the detected error condition. By monitoring the number of error bits and comparing it with a preset threshold, the system selects between a first error correction algorithm (for low error counts) and a second error correction algorithm (for high error counts), thereby achieving adaptability to different error conditions without significantly increasing device complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11949429B2Memory device, error correction device and error correction method thereof

Publication Date: 2024.04.02 MACRONIX INTERNATIONAL CO LTD

AI summary

A memory device, an error correction device and an error correction method thereof are provided. The error correction device includes a first error correction decoder and a second error correction decoder. The first error correction decoder performs at least one iteration of a first error correction operation on a data chunk, calculates a counting number of syndrome values equal to a set logic value generated in the at least one iteration of the first error correction operation, and generates a control signal according to the counting number. The second error correction decoder receives the control signal and determines whether to be activated to perform a second error correction operation on the data chunk or not according to the control signal. An error correction ability of the second error correction decoder is higher than an error correction ability of the first error correction decoder.