Adaptive Memory ECC for Multi-Bit Fault Reliability

The patent applies local quality by implementing error correction selectively only for memory pages that have exhibited errors, rather than uniformly across all memory. The system monitors individual memory pages and applies enhanced error correction (such as multi-bit ECC) only to those pages that show signs of degradation or have previously failed, while leaving other pages with standard error correction. This localized approach maintains high reliability for problematic areas without unnecessarily increasing device complexity and cost for the entire memory system.

The patent implements dynamics by making error correction capability adaptive and changeable over time. The system dynamically adjusts the level of error correction applied to memory pages based on their observed behavior and error history. Memory pages can transition between different error correction regimes (standard ECC, enhanced ECC, or no correction) as their reliability characteristics change during device operation. This dynamic adaptation allows the system to respond to actual wear and error patterns rather than using a static, over-engineered solution from the start.

The patent reduces power consumption by applying enhanced error correction only to specific memory pages that require it, rather than activating powerful error correction mechanisms across the entire memory space. The system identifies problematic pages through monitoring and applies resource-intensive correction algorithms only where necessary, allowing the majority of memory operations to proceed with standard, lower-power error correction. This localized application significantly reduces overall power consumption compared to universal RAS implementation.

The system dynamically adjusts power consumption by adapting error correction intensity to actual needs. When memory pages are healthy and error-free, the system uses minimal error correction with low power consumption. When errors are detected or predicted, the system activates enhanced error correction only for affected pages, increasing power usage temporarily and locally rather than maintaining high power consumption continuously across all memory. This dynamic power management aligns resource usage with actual reliability requirements.

The patent resolves this contradiction by applying different error correction capabilities to different memory pages based on their needs. Standard ECC is used for the majority of pages that show no signs of degradation, maintaining low device complexity. However, for pages that exhibit error patterns indicating susceptibility to multi-bit faults, the system applies enhanced error correction codes (such as multi-bit ECC or alternative algorithms) locally to those specific pages. This selective approach ensures adequate reliability for vulnerable pages without increasing overall device complexity.

The system dynamically transitions memory pages between standard and enhanced error correction regimes based on observed error patterns. Initially, pages use standard error correction with low complexity. When pages exhibit error characteristics (such as repeated single-bit errors or correction failures), the system dynamically upgrades their error correction capability to handle multi-bit faults. This dynamic adaptation ensures reliability is enhanced only when and where needed, avoiding the permanent complexity overhead of universal high-capability error correction.