Adaptive Memory ECC Based on Wear and Parity Bit Scaling
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Solution Overview
Problem
Conventional memory sub-systems use a fixed error correction code based on the worst-case scenario, leading to excessive parity bits at the beginning of their operating life, which reduces storage efficiency and increases wear due to unnecessary parity data writing.
Innovation Solution
Adaptive error correction codes are implemented based on the wear and usage of the memory sub-system, increasing the number of parity bits over time as the rate of errors increases, using a polar encoder and decoder to encode and decode data with a varying number of parity bits stored according to the memory's condition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed error correction code based on worst-case scenario is used, then error correction capability is improved, but storage efficiency deteriorates due to excessive parity bits
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed error correction code to a dynamic adaptive code that adjusts the number of parity bits based on memory wear level. The system monitors wear indicators and dynamically selects appropriate error correction codes, increasing parity bits only when necessary as memory degrades, thus optimizing both reliability and storage efficiency throughout the memory lifecycle.
Solution Approach 2:
The patent changes the parameter of error correction code strength based on memory wear conditions. Initially, when memory is new, a weaker error correction code with fewer parity bits is used to maximize storage efficiency. As memory wear increases and error rates rise, the system transitions to stronger error correction codes with more parity bits, adapting the code parameters to match the actual memory condition.
2Reliability
If excessive parity bits are written at the beginning of operating life, then error correction capability is improved, but memory wear increases due to unnecessary parity data writing
Solution Approach 1:
The system dynamically adjusts the number of parity bits written based on real-time wear monitoring. At the beginning of the memory's operating life, when wear is minimal, fewer parity bits are written, reducing unnecessary write operations. As wear accumulates and triggers wear indicators, the system increases parity bit writing to maintain reliability, thus optimizing memory endurance throughout its operational lifecycle.
Solution Approach 2:
The patent implements preliminary monitoring of memory wear conditions and proactively adjusts error correction code strength before catastrophic failures occur. By continuously tracking wear indicators and preemptively increasing parity bits when wear thresholds are approached, the system prevents sudden data loss while minimizing unnecessary parity writing during the healthy phase of memory operation.
3Quantity of substance
If adaptive error correction codes are implemented, then storage utilization is improved, but device complexity increases due to dynamic adjustment mechanisms
Solution Approach 1:
The patent implements feedback mechanisms that monitor memory wear indicators and automatically adjust error correction code strength accordingly. The system continuously reads wear status, compares it against predefined thresholds, and selects appropriate error correction codes without requiring complex external management. This feedback-driven approach simplifies the overall system architecture while achieving adaptive optimization of storage utilization and reliability.
Data Source
AI summary
Data to be stored at a memory sub-system can be received. A usage characteristic of the memory sub-system can be determined. The received data can be encoded to generate a codeword with a number of parity bits. A portion of the number of parity bits of the generated codeword can be removed based on the usage characteristic of the memory sub-system. Furthermore, the codeword can be stored without the removed portion of the number of parity bits.