Adaptive Memory Device Error Recovery by Failure Severity

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Solution Overview

Problem

Existing memory devices face performance issues due to inefficient error recovery operations, particularly when severe failures occur, leading to prolonged downtime and unnecessary stress on memory cells.

Innovation Solution

Adaptive error recovery operations are performed based on data state metrics, such as CFBit and CFByte counts, to predict whether less intensive read error handling (REH) or more intensive RAID recovery is necessary, optimizing the recovery process to improve performance and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If less intensive read error handling (REH) is performed, then memory device performance is improved and downtime is reduced, but recovery reliability deteriorates when severe failures occur

Engineering Contradiction:

Improvememory device performanceVSAvoidrecovery reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic selection of error recovery operations based on failure severity assessment. The system adapts the intensity of recovery operations (REH vs. RAID) according to the specific failure conditions detected, transitioning from static to dynamic error handling strategies to optimize both performance and reliability

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of recovery operation intensity based on failure characteristics. By assessing failure severity and selecting appropriate recovery methods (less intensive REH for minor failures, more intensive RAID for severe failures), the system optimizes the balance between recovery speed and recovery success rate

Inventive Principle:

Principle #35Parameter changes

2Reliability

If more intensive RAID recovery is performed, then recovery reliability is improved, but downtime increases and memory cells experience unnecessary stress

Engineering Contradiction:

Improverecovery reliabilityVSAvoiddowntime

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by selecting the minimum necessary recovery intensity based on failure severity. For minor failures, only less intensive REH is applied; for severe failures, more intensive RAID recovery is used. This avoids excessive recovery actions on minor failures, reducing unnecessary downtime and stress on memory cells

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If more intensive RAID recovery is performed, then recovery reliability is improved, but memory cells experience unnecessary stress

Engineering Contradiction:

Improverecovery reliabilityVSAvoidstress on memory cells

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies partial action by matching recovery intensity to failure severity. Less intensive REH is used for minor failures, avoiding the excessive stress that would be caused by RAID recovery. This selective approach minimizes harmful stress on memory cells while maintaining adequate recovery reliability

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS12386702B2Adaptive error recovery when program status failure occurs in a memory device

Publication Date: 2025.08.12 MICRON TECHNOLOGY INC

AI summary

A system and method for detecting a failure of a set of memory cells in a memory device, determining a recovery indicator associated the failure, the recovery indicator corresponding to a subset of cells of the set of memory cells, and the subset of cells having a threshold voltage above a read level, where the read level corresponds to a per-cell memory density of the plurality of cells of the memory device, determining a data recovery operation based on whether the recovery indicator satisfies a threshold condition, the threshold condition corresponding to the read level, and causing the data recovery operation to be performed on the set of memory cells.