Adaptive Memory Data Correction for Multi-Bank Failure Recovery
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Solution Overview
Problem
Conventional memory failure handling techniques, such as ADDDC, are inflexible and inefficient in managing multiple memory failures, leading to reduced error-correcting performance and increased server downtime due to the occupation of backup memory spaces, and are limited in handling more than two failures without triggering system calls.
Innovation Solution
Implementing a dynamic bank VLS and adaptive multiple DDC (AMDDC) approach that utilizes a modified region register with bank group information to dynamically manage memory failures, allowing for flexible handling of multiple failures by identifying and utilizing non-failed banks and ranks as backup regions, thereby extending the system's ability to recover from more failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ADDDC is used to handle memory failures, then two failures can be corrected, but the system cannot handle more than two failures and triggers system calls, reducing reliability
Solution Approach 1:
The patent implements dynamic bank virtual lock step device data correction that adapts its behavior based on the number and location of failures. The system dynamically switches between different correction modes (single device, double device, triple device) depending on the failure scenario, allowing flexible handling of any number of failures without triggering system calls.
Solution Approach 2:
The patent segments the memory correction process into multiple independent correction operations. Each failure can be handled separately through individual correction operations, allowing the system to manage multiple failures without being limited by a fixed correction capacity. This segmentation enables the system to handle more than two failures by applying corrections sequentially.
2Reliability
If backup memory spaces are occupied for failure handling, then error-correcting performance is maintained, but server downtime increases due to limited backup availability
Solution Approach 1:
The patent performs preliminary identification and mapping of backup memory regions before actual failures occur. The system pre-establishes correction operations and maps backup spaces, so when failures happen, the correction can be applied immediately without triggering system calls or causing downtime. This preliminary preparation ensures continuous operation while maintaining error-correcting performance.
3Ease of manufacture
If rigid memory failure handling is used, then implementation is simple, but adaptability to different failure scenarios is reduced
Solution Approach 1:
The patent implements a universal memory correction mechanism that can handle multiple failure scenarios through a single integrated system. The correction apparatus can perform single device correction, double device correction, and triple device correction using the same fundamental mechanism, eliminating the need for separate handling approaches for different failure types while maintaining implementation simplicity.
Data Source
AI summary
An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.